WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 147
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
Lead Free Status / Rohs Status
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Intel
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
15
17:16
21:18
22
23
24
25
26
30:27
31
Bit
RW
RW
RO
RW
RW
RO
RW
RW
RW
RO
Type
0b
00b
0x0
0b
0b
0b
0b
0b
0x0
0b
Reset
Broadcast Accept Mode (BAM).
0b = Ignore broadcast (unless it matches through exact or imperfect
filters).
1 = Accept broadcast packets.
Receive Buffer Size (BSIZE).
RCTL.BSEX – zero:
00b = 2048 bytes.
01b = 1024 bytes.
10b = 512 bytes.
11b = 256 bytes.
RCTL.BSEX – one:
00b = Reserved.
01b = 16384 bytes.
10b = 8192 bytes.
11b = 4096 bytes.
BSIZE is only used when DTYP – 00b. When DTYP – 01b, the buffer sizes
for the descriptor are controlled by fields in the PSRCTL register.
BSIZE is not relevant when the FLXBUF is other than zero, in that case,
FLXBUF determines the buffer size.
Reserved. Should be written with 0b.
Reserved.
Pass MAC Control Frames (PMCF).
0b = Do not (specially) pass MAC control frames.
1 = Pass any MAC control frame (type field value of 0x8808) that does not
contain the pause opcode of 0x0001.
Reserved. Should be written with 0b to ensure future compatibility.
Buffer Size Extension (BSEX).
Modifies buffer size indication (BSIZE).
0b = Buffer size is as defined in BSIZE.
1b = Original BSIZE values are multiplied by 16.
Strip Ethernet CRC from incoming packet (SECRC).
0b = Does not strip CRC.
1b = Strips CRC.
The stripped CRC is not DMA'd to host memory and is not included in the
length reported in the descriptor.
FLXBUF. Determines a flexible buffer size. When this field is 0000b, the
buffer size is determined by BSIZE. If this field is different from 0000b, the
receive buffer size is the number represented in KB:
For example, 0001 = 1 KB (1024 bytes).
Reserved. Should be written with 0b to ensure future compatibility.
Description
140
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