DT28F160S570 Intel, DT28F160S570 Datasheet - Page 10

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
2.1
Depending on the application, the system
designer may choose to make the V
supply switchable or hardwired to V
device supports either design practice, and
encourages
memory interface.
When V
altered. When high voltage is applied to V
two-step block erase, program, or lock-bit
configuration
protection from unwanted operations. All write
functions are disabled when V
the write lockout voltage V
V
provides additional protection from inadvertent
code or data alteration.
10
IL
.
The
during
PP
Data Protection
device’s
V
3FFFFF
1FFFFF
01FFFF
00FFFF
3F0000
1F0000
010000
000000
optimization
PPLK
command
flash
, memory contents cannot be
block
memory
Byte-Wide (x8) Mode
LKO
16-Mbit: A[
32-Mbit: A[
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
sequences
of
CC
locking
or when RP# is at
the
voltage is below
updates.
20-0
21-0
processor-
PP
PPH
capability
]
]
provide
Figure 4. Memory Map
PP
63
31
1
0
power
. The
After
, the
1FFFFF
0FFFFF
00FFFF
007FFF
1F0000
0F8000
008000
000000
3.0
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1
Block information, query information, identifier
codes
independent of the V
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE
active to obtain data at the outputs. CE
CE
when both are active, enable the selected
memory device. OE# is the data output (DQ
DQ
memory data onto the I/O bus. WE# must be at
V
a read cycle.
Word-Wide (x16) Mode
IH
1
15
and RP# must be at V
# are the device selection controls, and,
16-Mbit: A[
32-Mbit: A[
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
) control: When active it drives the selected
deep
BUS OPERATION
and
Read
power-down
status
20-1
21-1
0
#, CE
]
]
63
31
1
0
PP
1
registers
# and OE# must be driven
voltage.
PRELIMINARY
IH
16 Mbit
. Figure 16 illustrates
mode,
can
the
32 Mbit
be
0
device
# and
read
0609_04
0
–