DT28F160S570 Intel, DT28F160S570 Datasheet - Page 30

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
30
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
SR.4 = PROGRAM AND SET LOCK-BIT
SR.3 = V
SR.2 = PROGRAM SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS
SR.0 = RESERVED FOR FUTURE
XSR.7 = WRITE BUFFER STATUS
XSR.6–0 = RESERVED FOR FUTURE
ENHANCEMENTS
WSMS
WBS
1 = Ready
0 = Busy
1 = Block erase suspended
0 = Block erase in progress/completed
1 = Error in block erasure or clear lock-bits
0 = Successful block erase or clear lock-bits
1 = Error in program or block lock-bit
0 = Successful program or set block lock-bit
1 = V
0 = V
1 = Program suspended
0 = Program in progress/completed
1 = Block Lock-Bit and/or
0 = Unlock
1 = Write to buffer available
0 = Write to buffer not available
7
7
STATUS
WP# lock detected, operation abort
ENHANCEMENTS
PP
PP
PP
STATUS
low detect, operation abort
OK
ESS
R
6
6
Table 16. Extended Status Register Definition
ECLBS
R
5
5
Table 15. Status Register Definition
BWSLBS
R
4
4
NOTES:
Check STS in RY/BY# mode or SR.7 to determine
block erase, programming, or lock-bit configuration
completion. SR.6-0 are invalid while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block erase
or lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of
V
V
bit configuration operation. SR.3 reports accurate
feedback only when V
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bit, and WP# only after a block erase,
program, or lock-bit configuration operation. It
informs the system, depending on the attempted
operation, if the block lock-bit is set.
SR.0 is reserved for future use and should be
masked when polling the status register.
NOTES:
After a Write to buffer command, XSR.7 indicates
that another Write to buffer command is possible.
SR.6–0 are reserved for future use and should be
masked when polling the status register
PP
PP
VPPS
level. The WSM interrogates and indicates the
level only after a block erase, program, or lock-
3
R
3
BWSS
2
R
2
PP
= V
PRELIMINARY
PPH
DPS
1
R
1
.
R
0
R
0