DT28F160S570 Intel, DT28F160S570 Datasheet - Page 11

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3
CE
the device in standby mode, substantially
reducing device power consumption. DQ
(or DQ
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit
functioning and consuming active power until the
operation completes.
3.4
RP# at V
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the status register
is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data
programming or partially altered after an erase or
lock-bit configuration. Time t
RP# goes to logic-high (V
command can be written.
PRELIMINARY
0
# or CE
0
may
– DQ
IL
Output Disable
Standby
configuration,
Deep Power-Down
initiates the deep power-down mode.
1
7
# at a logic-high level (V
in x8 mode) outputs are placed in
be
PLPH
partially
. Time t
the
PHWL
IH
device
) before another
corrupted
PHQV
is required after
IH
), the device
0
is required
–DQ
IH
continues
) places
0
–DQ
15
after
are
15
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash
provide status information when accessed during
block
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
3.6
The read-identifier codes operation outputs the
manufacturer code, device code, and block lock
configuration codes for each block configuration
(see Figure 5). Using the manufacturer and
device
automatically match the device with its proper
algorithms. The block-lock configuration codes
identify each block’s lock-bit setting.
memory.
Flash
erase,
codes,
Read Query Operation
Read Identifier Codes
Operation
memories
Automated
the
programming,
system
28F160S5/28F320S5
allow
flash
software
proper
or
memories
lock-bit
CPU
can
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