DT28F160S570 Intel, DT28F160S570 Datasheet - Page 29

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

NOTE:
1.
Program and
Block Erase
Full Chip Erase
Set or Clear
Block Lock-Bit
DQ7–DQ2 = Reserved
DQ1/DQ0 = STS Pin Configuration Codes
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits D7–D2 to 00h) are as
follows:
Default RY/BY# level mode
ER INT (Erase Interrupt):
PR INT (Program Interrupt):
ER/PR INT (Erase or Program Interrupt): B8h, 03h
PRELIMINARY
Operation
00 = default, level mode RY/BY#
01 = pulse on Erase complete
10 = pulse on Flash Program complete
11 = pulse on Erase or Program Complete
When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
Pulse-on-Erase Complete
Pulse-on-Flash-Program Complete
Pulse-on-Erase or Program Complete
(device ready) indication
Block
Lock-
Bit
0,1
X
X
0
1
Table 14. Configuration Coding Definitions
V
IL
Table 13. Write Protection Alternatives
WP#
V
V
V
V
V
V
or V
Reserved
IH
IH
IH
IL
IL
IL
bits 7–2
IH
B8h, 00h
B8h, 01h
B8h, 02h
Block erase and programming enabled
Block is locked. Block erase and programming disabled
Block Lock-Bit override. Block erase and programming enabled
All unlocked blocks are erased
Block Lock-Bit override. All blocks are erased
Set or clear block lock-bit disabled
Set or clear block lock-bit enabled
DQ7–DQ2 are reserved for future use.
default (DQ1/DQ0 = 00) RY/BY#, level mode
configuration 01
configuration 10
configuration
—used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
—used to generate a system interrupt pulse when
any flash device in an array has completed a block
erase or sequence of queued block erases. Helpful
for reformatting blocks after file system free space
reclamation or ‘cleanup’
—used to generate a system interrupt pulse when
any flash device in an array has complete a
program operation. Provides highest performance
for servicing continuous buffer write operations.
servicing of flash arrays when either erase or flash
program operations are completed when a common
interrupt service routine is desired.
—used to generate system interrupts to trigger
Effect
Complete
ER INT, pulse mode
PR INT, pulse mode
ER/PR INT, pulse mode
Pulse on
28F160S5/28F320S5
Write
bit 1
Complete
Pulse on
Erase
bit 0
(1)
(1)
29
(1)