DT28F160S570 Intel, DT28F160S570 Datasheet - Page 38

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
5.0
5.1
Intel provides three control inputs to accommodate
multiple memory connections: CE
OE#, and RP#. Three-line control provides for:
To use these control inputs efficiently, an address
decoder should enable CEx# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs, while de-
selected memory devices are in standby mode.
RP#
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
STS is an open drain output that should be
connected to V
hardware form of detecting block erase, program,
and lock-bit configuration completion. In default
mode, it transitions low during execution of these
commands and returns to V
finished executing the internal algorithm. For
alternate STS pin configurations, see Section 4.10.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also V
is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3
Flash memory power switching characteristics
require careful device decoupling. Standby current
levels, active current levels and transient peaks
produced by falling and rising edges of CE
OE# are areas of interest. Two-line control and
proper decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
V
frequency, low-inductance capacitors should be
placed as close as possible to package leads.
38
CC
a. Lowest possible memory power dissipation;
b. Data bus contention avoidance.
and GND and V
should
DESIGN CONSIDERATIONS
Three-Line Output Control
STS and WSM Polling
Power Supply Decoupling
CC
be
by a pull-up resistor to provide a
connected
PP
and GND. These high-
OH
when the WSM has
OH
X
to
when the device
# (CE
the
0
#, CE
system
X
# and
1
#),
Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between V
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
5.4
Updating target-system resident flash memories
requires that the printed circuit board designer pay
attention to V
supplies the memory cell current for programming
and block erasing. Use similar trace widths and
layout considerations given to the V
Adequate V
decrease V
5.5
Block erase, program, and lock-bit configuration are
not guaranteed if RP#
outside of a valid voltage range (V
If V
SR.4 or SR.5 are set to “1.” If RP# transitions to V
during
configuration, STS in level RY/BY# mode will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. Because the aborted
operation may leave data partially altered, the
command sequence must be repeated after normal
operation is restored.
5.6
The device offers protection against accidental
block erase, programming, or lock-bit configuration
during power transitions.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE
command write, driving either input signal to V
inhibit writes. The CUI’s
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. RP# = V
the device regardless of its control inputs states.
PP
error is detected, status register bit SR.3 and
block
Boards
V
Power-Up/Down Protection
V
PP
CC
PP
CC
PP
PP
voltage spikes and overshoots.
, V
Trace on Printed Circuit
voltages above V
supply traces and decoupling will
power supply traces. The V
erase,
PP
, RP# Transitions
PRELIMINARY
V
program,
IH,
or if V
two-step command
X
# must be low for a
LKO
CC1/2
CC
PP
CC
when V
or
power bus.
or V
and V
IL
and GND.
disables
lock-bit
CC
PP
IH
PP
PPH
will
pin
fall
is
IL
).