LH28F016SCHR-L95 Sharp Electronics, LH28F016SCHR-L95 Datasheet - Page 9

• Manufacturer Part Number: LH28F016SCHR-L95
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCHR-L95

• Cell Type: NOR
• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

16M Flash Memory
Read Array Command
deep power-down mode, the device defaults to Read
Array mode. This operation is also initiated by writing
the Read Array command. The device remains
enabled for reads until another command is written.
Once the internal WSM has started a block erase, byte
write or block lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended
via an Erase Suspend or Byte Write Suspend com-
mand. The Read Array command functions indepen-
dently of the V
Read Identifier Codes Command
Read Identifier Codes command. Following the com-
mand write, read cycles from addresses shown in Fig-
ure 4 retrieve the manufacturer, device, block lock
configuration and master lock configuration codes (see
Table 5 for identifier code values). To terminate the
operation, write another valid command, such as a
Read Array command. The Read Identifier Codes com-
mand functions independently of the V
RP must be at V
Identifier Codes command, the information can be read:
NOTE: *‘x’ Selects the specific block lock configuration code to be
Data Sheet
Manufacturer Code
Device Code
Block Lock Configuration
Block is Unlocked
Block is Locked
Reserved for Future Use
Master Lock Configuration
Block is Unlocked
Device is Locked
Reserved for Future Use
Upon initial device power-up and after exit from
The identifier code operation is initiated by writing the
read. See Figure 4 for the device identifier code memory map.
CODE
Table 5. Identifier Codes
PP
IH
voltage and RP must be V
or V
HH
. After issuing the the Read
ADDRESS
x0002*
00000
00001
00003
PP
voltage and
DQ
DQ
IH
DQ
DQ
DQ
DQ
DATA
7
7
or V
AA
89
0
0
= DQ
0
0
= DQ
= 0
= 1
= 0
= 1
HH
1
1
.
Read Status Register Command
a block erase, byte write or block lock bit configuration
is complete and whether the operation completed suc-
cessfully. It may be read at any time by writing the
Read Status Register command. After writing this com-
mand, all subsequent read operations output data from
the status register until another valid command is writ-
ten. The status register contents are latched on the fall-
ing edge of OE or CE whichever occurs first. OE or CE
must toggle to V
status register latch. The Read Status Register com-
mand functions independently of the V
must be V
Clear Status Register Command
are set to ‘1’ by the WSM, they can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 7). By allowing
system software to reset these bits, several operations
(such as cumulatively erasing or locking multiple
blocks or writing several bytes in sequence) may be
performed. The status register may be polled to deter-
mine if an error occurred during the sequence.
ter command (50H) is written. It functions indepen-
dently of the applied V
V
erase or byte write suspend modes.
Block Erase Command
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This com-
mand sequence requires appropriate sequencing plus
an address within the block to be erased (erase
changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM
(invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure 5).
The CPU can detect block erase completion by analyz-
ing the output data of the RY/BY pin or status register
bit SR.7. When the block erase is complete, status reg-
ister bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until a
new command is issued.
HH
The status register may be read to determine when
When status register bits SR.5, SR.4, SR.3, or SR.1
To clear the status register, the Clear Status Regis-
Erase is executed one block at a time and initiated
. This command does not function during block
IH
or V
HH
IH
.
before further reads to update the
PP
voltage. RP can be V
LH28F016SCT
PP
voltage. RP
IH
or
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