TE28F800B3B110 Intel, TE28F800B3B110 Datasheet - Page 40

• Manufacturer Part Number: TE28F800B3B110
• Manufacturer: Intel

Specifications of TE28F800B3B110

• Lead Free Status / Rohs Status: Not Compliant

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 18.
Figure 10.
18 Aug 2005
40
Read Operations — 64-Mbit Density
Read Operation Waveform
Notes:
1.
2.
3.
4.
R10
Address [A]
R1
R2
R3
R4
R5
R6
R7
R8
R9
Data [D/Q]
#
RST# [P]
WE# [W]
OE# [G]
CE# [E]
t
t
t
t
t
t
t
t
OE# can be delayed up to t
Sampled, but not 100% tested.
See
See
maximum allowable input slew rate.
t
Sym
GLQV
PHQV
GLQX
EHQZ
GHQZ
AVQV
ELQV
ELQX
AVAV
t
OH
Figure 10 “Read Operation Waveform” on page
Figure 12 “AC Input/Output Reference Waveform” on page 46
Intel
Read Cycle Time
Address to Output Delay
CE# to Output Delay
OE# to Output Delay
RP# to Output Delay
CE# to Output in Low Z
OE# to Output in Low Z
CE# to Output in High Z
OE# to Output in High Z
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
®
Order Number: 290580, Revision: 020
Advanced Boot Block Flash Memory (B3)
Parameter
R6
ELQV–
R5
R2
R3
t
GLQV
after the falling edge of CE# without impact on t
R7
Product
R4
Density
V
CC
R1
R1
40.
Note
1,3,4
1,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
3,4
3,4
3,4
2.7 V–3.6 V
Min
70
0
0
0
70 ns
for timing measurements and
Max
150
70
70
20
20
20
64 Mbit
2.7 V–3.6 V
Min
80
0
0
0
80 ns
ELQV
Max
150
80
80
20
20
20
R8
Datasheet
R10
R9
.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns