TE28F800B3B110 Intel, TE28F800B3B110 Datasheet - Page 54

• Manufacturer Part Number: TE28F800B3B110
• Manufacturer: Intel

Specifications of TE28F800B3B110

• Lead Free Status / Rohs Status: Not Compliant

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
11.1
Table 28.
18 Aug 2005
54
00, 01,
60, 2F,
C0, 98
Code
FF
D0
40
10
20
Program Set-Up
Program Set-Up
Program / Erase
Erase Confirm
Device Mode
Erase Set-Up
Read Array
Read Array
When RP# transitions from V
mode and responds to the read-control inputs (CE#, address inputs, and OE#) without any
additional CUI commands.
When the flash memory device is in read-array mode, four control signals control data output:
In addition, the address of the preferred location must be applied to the address pins. If the flash
memory device is not in read-array mode, such as after a Program or Erase operation, the Read
Array command (FFH) must be written to the CUI before array reads can occur.
Command Codes and Descriptions (Sheet 1 of 2)
Reserved
Alternate
Resume
Invalid/
•
•
•
•
WE# must be logic high (V
CE# must be logic low (V
OE# must be logic low (V
RP# must be logic high (V
Unassigned commands that must not be used. Intel reserves the right to redefine these codes
for future functions.
Places the flash memory device in read-array mode, so that array data is output on the data
pins.
A two-cycle command.
The flash memory device outputs Status Register data when CE# or OE# is toggled. To read
array data, a Read Array command is required after programming. See
(See 40H/Program Set-Up)
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI does the following:
1.
2.
3.
See
If the previous command was an Erase Set-Up command, then the CUI closes the address and
data latches, and begins erasing the block indicated on the address pins.
During erase, the flash memory device responds only to the Read Status Register and Erase
Suspend commands. The device outputs Status Register data when CE# or OE# is toggled.
If a Program or Erase operation was previously suspended, this command resumes that
operation.
Intel
• The first cycle prepares the CUI for a program operation.
• The second cycle latches addresses and data information, and initiates the WSM to
execute the program algorithm.
Section 11.5, “Erase Mode” on page
®
Order Number: 290580, Revision: 020
Sets both SR.4 and SR.5 of the Status Register to 1.
Places the flash memory device into the read-Status Register mode.
Waits for another command.
Advanced Boot Block Flash Memory (B3)
IL
IL
IL
IH
IH
(reset) to V
)
)
)
)
IH
, the flash memory device defaults to read-array
Description
58.
Section
11.4.
Datasheet