TE28F800B3T90 Intel, TE28F800B3T90 Datasheet - Page 47

• Manufacturer Part Number: TE28F800B3T90
• Manufacturer: Intel

Specifications of TE28F800B3T90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

9.0
9.1
9.1.1
9.1.2
Datasheet
Power and Reset Specifications
Power-Up/Down Characteristics
To prevent any condition that might result in a spurious write or erase operation, power-up V
and V
Also power-up V
before V
If V
applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin.
Power supply transitions must occur only when RP# is low.
RP# Connected to System Reset
Use RP# during system reset with automated program/erase devices, because the system expects to
read from the flash memory when the system exits reset. If a CPU reset occurs without a flash
memory reset, proper CPU initialization does not occur, because the flash memory might be
providing status information instead of array data. Connecting RP# to the system CPU RESET#
signal to allow proper CPU/flash initialization after a system reset.
System designers must guard against spurious writes when V
both WE# and CE# must be low for a command write, driving either signal to V
the flash memory device. The CUI architecture provides additional protection, because memory
contents can be altered only after successful completion of the two-step command sequences. The
flash memory device is also disabled until RP# is brought to V
control inputs. By holding the device in reset (RP# connected to system POWERGOOD) during
power-up/down, invalid bus conditions during power-up can be masked, providing yet another
level of memory protection.
V
The CUI latches commands as issued by system software, and is not altered by V
transitions or WSM actions. The CUI default state upon power-up, after exit from reset mode or
after V
After any program or Block-Erase operation is complete (even after V
V
flash-memory array is required.
PPLK
CC
CCQ
, V
CCQ
), the CUI must be reset to read-array mode, using the Read Array command if access to the
CC
CC
and/or VPP are not connected to the V
PP,
transitions above V
together. Conversely, V
.
and RP# Transitions
Intel
PP
®
with or slightly after V
Order Number: 290580, Revision: 020
Advanced Boot Block Flash Memory (B3)
LKO
CC
(Lockout voltage), is read-array mode.
and V
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
CC
CCQ
. Conversely, V
CC
must power-down together.
supply, then V
CC
PP
IH
voltages are above V
must power-down with or slightly
, regardless of the state of its
CC
must attain V
PP
transitions down to
IH
PP
inhibits writes to
CC
or CE#
Min before
LKO
18 Aug 2005
. Because
CC
47