TE28F800F3B95 Intel, TE28F800F3B95 Datasheet - Page 14

• Manufacturer Part Number: TE28F800F3B95
• Manufacturer: Intel

Specifications of TE28F800F3B95

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
3.1.3
3.1.4
3.1.5
8
Standby
Deselecting the device by bringing CE# to a logic-high level (V
mode, which substantially reduces device power consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If deselected during program or erase operation, the
device continues to consume active power until the program or erase operation is complete.
Write
Commands are written to the CUI using standard microprocessor write timings when ADV#, WE#,
and CE# are active and OE# is inactive. The CUI does not occupy an addressable memory location.
The address is latched on the rising edge of ADV#, WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous. Therefore, CLK is ignored during write operations.
Figure 20, “AC Waveform for Write Operations” on page 39
Reset
The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After return from reset, a time t
is required before a write sequence can be initiated. After this wake-up interval, normal operation
is restored. The device defaults to read array mode, the status register is set to 80H, and the read
configuration register defaults to asynchronous page-mode reads.
If RST# is taken low during a block erase or program operation, the operation will be aborted and
the memory contents at the aborted location are no longer valid. See
Reset Operation” on page 40
for detailed information regarding reset timings.
PHQV
is required until outputs are valid, and a delay (t
illustrates a write operation.
IH
) places the device in standby
Figure 21, “AC Waveform for
PRELIMINARY
PHWL
or t
PHEL
)