TE28F800F3B95 Intel, TE28F800F3B95 Datasheet - Page 23

• Manufacturer Part Number: TE28F800F3B95
• Manufacturer: Intel

Specifications of TE28F800F3B95

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

4.9.3
PRELIMINARY
Table 7. Frequency Configuration Settings
NOTE: Table derived by using formulas (1), (2) and (3) in
Data Output Configuration – (RCR.9)
The output configuration determines the number of clocks during which data will be held valid.
The data hold time is configurable as either one or two clocks.
Subsequent reads in burst mode with zero wait-states can be defined by:
In
applied to the formula above for the subsequent reads assuming the data output hold time is one
clock:
Data output will be available and valid at every clock period.
Consider the CPU frequency at 60 MHz, and FCC is 5. Clock period is 16.6 ns. The initial access
time is calculated to be 125 ns (5 latencies). This condition satisfies t
(ns) = 95 ns + 6 ns + 4 ns = 105 ns. However, the data output hold time of one clock violates burst
data output zero wait-states:
19 ns + 4 ns = 23 ns is not less than one clock period. To satisfy the formula above the data output
hold time must be set a 2 clocks to correctly allow for data output setup time.
In page mode reads the initial access time can be determined by the formula:
and subsequent reads in page mode are defined by:
Frequency Configuration Code
Table
assumed to be 6 ns and 4 ns respectively; value of t
7, consider the CPU clock at 40 MHz, and FCC is 3. The clock period is 25 ns. This data
t
19 ns + 4 ns 25 ns
t
t
t
CHQV
CHQV
ADD
APA
(ns) + t
(ns) + t
(ns) + t
(ns) + t
1
2
3
4
5
6
DATA
DATA
DATA
DATA
(ns)
(ns) + t
(ns) One CLK Period
(ns) One CLK Period
AVQV
(minimum time)
(ns)
Reserved
38 MHz
47 MHz
57 MHz
66 MHz
–80
—
Section
AVQV
Input CLK Frequency
per
4.9.2. Values of t
Section
AVQV
8.5.
28F800F3—Automotive
ADD
(ns) + t
, t
Reserved
DATA
29 MHz
37 MHz
44 MHz
51 MHz
59 MHz
–95
ADD
defined by CPU,
(ns) + t
DATA
17