TE28F800F3B95 Intel, TE28F800F3B95 Datasheet - Page 18

• Manufacturer Part Number: TE28F800F3B95
• Manufacturer: Intel

Specifications of TE28F800F3B95

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
4.6
12
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = ERASE SUSPEND STATUS (ESS)
SR.5 = ERASE STATUS (ES)
SR.4 = PROGRAM STATUS (PS)
SR.3 = V
SR.2 = PROGRAM SUSPEND STATUS (PSS)
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure
0 = Successful Block Erase
1 = Error in Program
0 = Successful Program
1 = V
0 = V
1 = Program Suspended
0 = Program in Progress/Completed
1 = Block Erase or Program Attempted on a Locked Block,
Operation Abort
0 = Unlocked
Table 5.
7
PP
PP
PP
Low Detect, Operation Abort
OK
STATUS (VPPS)
Status Register Definition
Program Command
Program operation is executed by a two-cycle command sequence. Program setup (standard 40H or
alternate 10H) is written, followed by a second write that specifies the address and data. The WSM
then takes over, controlling the internal program algorithm. After the program sequence is written,
the device automatically outputs status register data when read (see
Flowchart” on page
status register bit SR.7.
When the program operation completes, check status register bit SR.4 for an error flag (“1”). If an
error is detected, check status register bits SR.5, SR.3, and SR.1 to understand what caused the
problem. After examining the status register, it should be cleared if an error was detected before
issuing a new command. The device will remain in status register read mode until another
command is written to the CUI.
ESS
6
ES
5
21). The CPU can detect the completion of the program event by analyzing
PS
4
NOTES:
Check SR.7 to determine block erase or program completion.
SR.6–0 are invalid while SR.7 = “0.”
When an Erase Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.6 to “1.” SR.6 remains
set until an Erase Resume command is written to the CUI.
If both SR.5 and SR.4 are “1”s after a block erase or program
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous V
interrogates and indicates the V
or program operation. SR.3 is not guaranteed to report
accurate feedback when V
When a Program Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.2 to “1.” SR.2 remains
set until a Program Resume command is written to the CUI.
If a block erase or program operation is attempted on a locked
block, SR.1 is set by the WSM and aborts the operation if
WP# = V
when polling the status register.
SR.0 is reserved for future use and should be masked out
VPPS
3
IL
.
PSS
2
PP
Figure 8, “Automated Program
V
PP
PPH1/2
level only after a block erase
DPS
PP
1
or V
feedback. The WSM
PPLK
PRELIMINARY
.
R
0