CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 10

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. Unlike global control signals, these OCC signal can
be driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
Document #: 38-03039 Rev. *I
Output PIM
To Routing
Channel
From
Figure 8. Block Diagram of I/O Cell
Input
Mux
2
3
3
C
C
C
C
Clock Mux
Register Reset
Mux
Register Enable
Mux
Polarity
Clock
Mux
C
C
Register Input
Mux
Table 3.
OE Mux
3
LVCMOS18
C
LVCMOS3
LVCMOS2
D
E
Standard
LVCMOS
3.3V PCI
SSTL3 II
SSTL2 II
HSTL IV
SSTL3 I
SSTL2 I
HSTL III
HSTL II
RES
HSTL I
LVTTL
GTL+
Q
I/O
Output Mux
D
C
RES
Q
Min.
1.15
1.15
0.68
0.68
0.68
0.68
Control
0.9
1.3
1.3
Registered OE
Slew
Rate
C
V
Mux
C
REF
N/A
I/O Standards
Hold
Bus
C
(V)
Max.
1.35
1.35
Delta39K™ ISR™
1.1
1.7
1.7
0.9
0.9
0.9
0.9
I/O
CPLD Family
V
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
N/A
CCIO
Voltage (V
Termination
Page 10 of 86
1.25
1.25
0.75
0.75
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.5
1.5
TT
)