CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 20

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Cluster Memory Timing Parameter Descriptions
Channel Memory Timing Parameter Descriptions
Document #: 38-03039 Rev. *I
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Dual Port Synchronous Mode Parameters
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Synchronous FIFO Data Parameters
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Synchronous FIFO Flag Parameters
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MACCLMS2
CLMCLAA
Internal Parameters
CHMAA
CHMPWE
CHMSA
CHMHA
CHMSD
CHMHD
CHMBA
CHMCYC1
CHMCYC2
CHMS
CHMH
CHMDV1
CHMDV2
CHMBDV
CHMMACS1
CHMMACS2
MACCHMS1
MACCHMS2
CHMCLK
CHMFS
CHMFH
CHMFRDV
CHMMACS
MACCHMS
CHMFO
CHMMACF
CHMFRS
CHMFRSR
CHMFRSF
CHMSKEW1
CHMSKEW2
CHMSKEW3
Dual Port Asynchronous Mode Parameters
Parameter
Parameter
Macrocell clock to cluster memory output clock in the same cluster
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Channel memory access time. Delay from address change to Read data out
Write enable pulse width
Address set-up to the beginning of Write enable with both signals from the same I/O block
Address hold after the end of Write enable with both signals from the same I/O block
Data set-up to the end of Write enable
Data hold after the end of Write enable
Channel memory asynchronous dual port address match (busy access time)
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data.
Channel memory synchronous dual-port address match (busy, clock to data valid)
Channel memory input clock to macrocell clock in the same cluster
Channel memory output clock to macrocell clock in the same cluster
Macrocell clock to channel memory input clock in the same cluster
Macrocell clock to channel memory output clock in the same cluster
Read and Write minimum clock cycle time
Data, Read enable, and Write enable set-up time relative to pin inputs
Data, Read enable, and Write enable hold time relative to pin inputs
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
Channel memory FIFO Read clock to macrocell clock for Read data
Macrocell clock to channel memory FIFO Write clock for Write data
Read or Write clock to respective flag output at output pins
Read or Write clock to macrocell clock with FIFO flag
Master Reset Pulse Width
Master Reset Recovery Time
Master Reset to Flag and Data Output Time
Read/Write Clock Skew Time for Full Flag
Read/Write Clock Skew Time for Empty Flag
Read/Write Clock Skew Time for Boundary Flags
Over the Operating Range (continued)
Over the Operating Range
Description
Description
Delta39K™ ISR™
CPLD Family
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