CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 3

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

General Description
The Delta39K family, based on a 0.18-mm, six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
Document #: 38-03039 Rev. *I
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
Cluster
Cluster
Cluster
PLL and Clock MUX
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
PIM
PIM
PIM
Cluster
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
RAM
RAM
LB 7
LB 6
LB 5
LB 4
RAM
4
LB 7
LB 6
LB 5
LB 4
4
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
GCTL[3:0]
Cluster
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
RAM
LB 0
LB 1
LB 2
LB 3
I/O Bank 2
I/O Bank 7
PIM
PIM
PIM
Cluster
Cluster
Cluster
RAM
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Cluster
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
RAM
RAM
LB 0
LB 1
LB 2
LB 3
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See Figure 1
for a block diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
PIM
PIM
PIM
Cluster
Cluster
Cluster
RAM
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Cluster
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
RAM
RAM
LB 0
LB 1
LB 2
LB 3
RAM
LB 0
LB 1
LB 2
LB 3
Delta39K™ ISR™
I/O Bank 3
I/O Bank 6
PIM
PIM
PIM
Cluster
Cluster
Cluster
RAM
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
RAM
LB 7
LB 6
LB 5
LB 4
RAM
CPLD Family
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
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