CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 19

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Switching Characteristics — Parameter Descriptions
Cluster Memory Timing Parameter Descriptions
Document #: 38-03039 Rev. *I
t
t
PLL Parameters
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t
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t
f
f
f
P
f
JTAG Parameters
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t
t
t
t
t
t
t
t
t
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t
Synchronous Mode Parameters
t
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Parameter
CKIN
IOREGPIN
MCCJ
DWSA
DWOSA
LOCK
INDUTY
PLLI
PLLO
PLLVCO
MPLLI
JCKH
JCKL
JCP
JSU
JH
JCO
JXZ
JZX
CLMAA
CLMPWE
CLMSA
CLMHA
CLMSD
CLMHD
CLMCYC1
CLMCYC2
CLMS
CLMH
CLMDV1
CLMDV2
CLMMACS1
CLMMACS2
MACCLMS1
Asynchronous Mode Parameters
SAPLLI
Parameter
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
Input duty cycle
Input frequency of the PLL
Output frequency of the PLL
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the f
(1–P
TCLK HIGH time
TCLK LOW time
TCLK clock period
JTAG port set-up time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
SAPLLI
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
/100) and f
PLLI
* (1+ P
SAPLLI
/100)
Over the Operating Range
Description
Description
Over the Operating Range
Delta39K™ ISR™
PLLI
[13]
sweeps between f
(continued)
CPLD Family
Page 19 of 86
PLLI
*