CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 12

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Table 6 describes the valid phase shift options that can be
used with or without an external feedback.
Table 7 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Table 6. Recommended PLL Phase Shift Options
Table 7. Timing of Clock Phases for all Divide Options for a V
Document #: 38-03039 Rev. *I
DC–12.5
100–133
50–133
33.3–88.7
25–66
20–53.2
16.6–44.3
12.5–33
12.5–16.625
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
Input (GCLK) Frequency
Divide
Factor
16
1
2
3
4
5
6
8
Input Frequency
f
(GCLK[0])
PLLI
f
PLLI
Period
(MHz)
(ns)
(MHz)
12
16
20
24
32
64
4
8
Duty Cycle%
40–60
33–67
40–60
50
50
50
50
50
Value
Without External Feedback
N/A
Valid Multiply Options
16
Value
1
2
3
4
5
6
8
1
1
1
1
1
1
1
Valid Multiply Options
Frequency (MHz)
(ns)
VCO Output
0°
0
0
0
0
0
0
0
0
Frequency (MHz)
100–133
100–266
100–266
100–266
100–266
100–266
100–266
200–266
VCO Output
N/A
100–266
100–266
100–266
100–266
125–266
150–266
200–266
(ns)
45°
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
(ns)
90°
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
Value
N/A
Value
For more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
CO
135°
(ns)
1
2
3
4
5
6
8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Output Frequency of 250 MHz
100–266
50–133
33.33–88.66
25–66.5
25–53.2
25–44.34
25–33.25
Output Frequency (INTCLK[3:0])
Output (INTCLK) Frequency
180°
(ns)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Valid Divide Options
f
f
Valid Divide Options
PLLO
PLLO
6.25–133
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
DC–12.5
(MHz)
(MHz)
225°
(ns)
0°
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Delta39K™ ISR™
With External Feedback
CPLD Family
270°
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
Off-chip Clock
DC–6.25
3.125–66
3.125–133
3.1–266
3.125–133
3.1–133
3.1–133
3.125–133
3.125–133
Off-chip Clock
Frequency
Frequency
Page 12 of 86
315°
(ns)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5