MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 106
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MC68EC040RC25
Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040RC25.pdf
(442 pages)
Specifications of MC68EC040RC25
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed
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5.1 ADDRESS BUS (A31–A0)
These three-state bidirectional signals provide the address of the first item of a bus
transfer (except for acknowledge transfers) when the M68040 is the bus master. When an
alternate bus master is controlling the bus, the processor examines (snoops) these signals
to determine whether the processor should intervene in the access to maintain cache
coherency.
The level on CDIS can select a multiplexed bus mode during processor reset, which
allows the address bus and data bus to be physically tied together for multiplexed bus
5-4
ATTRIBUTES
TRANSFER
TRANSFER
TRANSFER
NOTES:
DATA BUS
ADDRESS
CONTROL
CONTROL
MASTER
1. This signal is only available on the MC68040.
2. This signal is not available on the MC68EC040 and MC68EC040V.
3. These signals are different on power-up for the MC68LC040 and MC68EC040.
4. These signals are not available on the MC68040V and MC68EC040V.
SLAVE
BUS
Freescale Semiconductor, Inc.
Figure 5-1. Functional Signal Groups
D31–D0
A31–A0
DLE 1
For More Information On This Product,
TT0
TT1
R/W
LOCK
TM0
TM1
TM2
TLN0
TLN1
UPA0
UPA1
LOCKE
CIOUT
TS
TIP
TA
TEA
TCI
TBI
SIZ0
SIZ1
M68040 USER’S MANUAL
Go to: www.freescale.com
MC68040
SC0
SC1
M I
BR
BG
BB
CDIS
MDIS 2
RSTI
RSTO
IPEND
IPL1 3
PST0
PST1
PST2
PST3
IPL0 3
IPL2 3
AVEC
BCLK
PCLK 4
V
GND
TCK
TMS
TDI
TDO
TRST 4
CC
BUS SNOOP CONTROL
AND RESPONSE
BUS ARBITRATION
PROCESSOR
CONTROL
INTERRUPT
CONTROL
STATUS AND
CLOCKS
TEST
POWER SUPPLY
MOTOROLA
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