MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 205
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MC68EC040RC25
Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040RC25.pdf
(442 pages)
Specifications of MC68EC040RC25
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Freescale Semiconductor, Inc.
7.9.3 Snoop Read Cycle (Intervention Required)
If snooping is enabled for a read access and the corresponding data cache line contains
dirty data, the M68040 inhibits memory and responds to the access as a slave device to
supply the requested read data. Intervention in a byte, word, or long-word access is
independent of which long-word entry in the cache line is dirty. Figure 7-42 illustrates an
alternate bus master line read that hits a dirty line in the M68040 data cache. The
processor asserts TA to acknowledge the transfer of data to the alternate bus master, and
the data bus is driven with the four long words of data for the line. The timing illustrated is
for a best-case response time. Variations in the timing required by snooping logic to
access the caches can delay the assertion of TA by up to two additional clocks.
7.9.4 Snoop Write Cycle (Intervention Required)
If snooping with sink data is enabled for a byte, word, or long-word write access and the
corresponding data cache line contains dirty data, the M68040 inhibits memory and
responds to the access as a slave device to read the data from the bus and update the
data cache line. The dirty bit is set for the long word changed in the cache line. Figure
7-43 illustrates a long-word write by an alternate bus master that hits a dirty line in the
M68040 data cache. The processor asserts TA to acknowledge the transfer of data from
the alternate master, and the processor reads the value on the data bus. The timing
illustrated is for a best-case response time. Variations in the timing required by snooping
logic to access the caches can delay the assertion of TA by up to two additional clocks.
MOTOROLA
M68040 USER’S MANUAL
7- 63
For More Information On This Product,
Go to: www.freescale.com
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