MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 197

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.8.2.3 M68040 SYNCHRONOUS DMA ARBITRATION. Figure 7-37 illustrates a system
with an M68040 and a synchronous direct memory access (DMA) that contains an
M68040 interface. Figure 7-37(a) illustrates that the DMA owning the bus only when the
M68040 has no pending requests, and Figure 7-37(b) illustrates the DMA having higher
priority than the M68040 causing the M68040 to yield the bus to the DMA at any time
except when the M68040 is performing a locked bus operation. In either case, the M68040
is the default bus master; if there are no pending requests from either device, the external
arbiter gives the bus to the M68040. Similar to the M68040 fairness arbitration example,
the restriction on using LOCKE applies to this example.
MOTOROLA
BR2
NOTES:
1.
2.
LOCK
Because this example uses two MC68040s, 1 or 2 refers to the processor and its signals.
*Indicates the signal is asserted for that device.
STATE D
BR2* V
Figure 7-36. Dual M68040 Prioritized Arbitration State Diagram
LOCKE*
BB
STATE A
BR2*
BG1*, BG2
BG1*, BG2
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BB*
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M68040 USER’S MANUAL
BR2
BB
V BR2
BR1
BB
LOCK
LOCK
BR2
BR2*
LOCK*
LOCKE
LOCKE*
BG1, BG2*
BG1, BG2*
BB*
STATE C
BB
BR2 V BR1*
LOCK
STATE B
LOCK* V BB &
BR2*
LOCKE
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