MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 258
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MC68EC040RC25
Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040RC25.pdf
(442 pages)
Specifications of MC68EC040RC25
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed
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The three additional bits beyond the extended-precision format, the difference between
the intermediate result’s 67-bit mantissa and the stored result’s 64-bit mantissa, allow the
FPU to perform all calculations as though it were performing calculations using a float
engine with infinite bit precision. The result is always correct for the specified destination’s
data format before performing rounding (unless an overflow or underflow error occurs).
The specified rounding operation then produces a number that is as close as possible to
the infinitely precise intermediate value and still representable in the selected precision.
9-14
RN
ROUND AND STICKY = 0
ROUND OR STICKY = 1
GUARD AND LSB = 1,
ADD 1 TO
GUARD = 1
LSB
OR
Figure 9-8. Rounding Algorithm Flowchart
Freescale Semiconductor, Inc.
ADD 1 TO EXPONENT
SHIFT MANTISSA
For More Information On This Product,
RIGHT 1 BIT,
POS
INTERMEDIATE
RM
M68040 USER’S MANUAL
RESULT
Go to: www.freescale.com
NEG POS
ADD 1 TO
OVERFLOW = 1
LSB
INTERMEDIATE
SELECT ROUNDING MODE
RP
RESULT
INEX2 1
ROUND 0
GUARD 0
STICKY 0
NEG
ENTRY
EXIT
AND STICKY ARE
GUARD, ROUND,
AND STICKY BITS = 0
CHOPPED
RZ
GUARD, ROUND,
EXACT RESULT
EXIT
MOTOROLA
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