AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 43

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

6.4
SMM is one of the major operating modes, along with
Protected mode, Real mode, and Virtual mode. Figure
27 shows how the processor can enter SMM from any
of the three modes and then return.
The external signal SMI causes the processor to switch
to SMM. The RSM instruction exits SMM. SMM is trans-
parent to applications, programs, and operating sys-
tems for the following reasons:
Similar to Real mode, SMM has no privilege levels or
address mapping. SMM programs can execute all I/O
and other system instructions and can address up to
4 Gbyte of memory.
6.5
The RSM instruction (opcode 0F AAh) leaves SMM and
returns control to the interrupted program. The RSM
instruction can be executed only in SMM. An attempt to
execute the RSM instruction outside of SMM generates
an invalid opcode exception. When the RSM instruction
is executed and the processor detects invalid state in-
formation during the reloading of the save state, the
Reset
The only way to enter SMM is via a type of non-
maskable interrupt triggered by an external signal
The processor begins executing SMM code from a
separate address space, referred to earlier as sys-
tem management RAM (SMRAM)
Upon entry into SMM, the processor saves the reg-
ister state of the interrupted program (depending on
the save mode) in a part of SMRAM called the SMM
context save space
All interrupts normally handled by the operating sys-
tem or applications are disabled upon SMM entry
A special instruction, RSM, restores processor reg-
isters from the SMM context save space and returns
control to the interrupted program
Figure 27. Transition to and from SMM
Entering System Management Mode
Exiting System Management Mode
Reset
PE=0
VM=0
or
Protected
mode
mode
Virtual
mode
Real
VM=1
PE=1
Reset
RSM
RSM
RSM
SMI
or
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
SMI
Management
SMI
System
mode
processor enters the shutdown state. This occurs in the
following situations:
In Shutdown mode, the processor stops executing in-
structions until an NMI interrupt is received or reset ini-
tialization is invoked. The processor generates a
shutdown bus cycle.
Three SMM features can be enabled by writing to control
slots in the SMRAM state save area:
1. Auto HALT Restart. It is possible for the SMI re-
2. I/O Trap Restart. If the SMI was generated on an
3. SMBASE Relocation. The system can relocate the
A RESET also causes execution to exit from SMM.
6.6
When an SMI signal is recognized on an instruction ex-
ecution boundary, the processor waits for all stores to
complete, including emptying the write buffers. The final
write cycle is complete when the system returns RDY
or BRDY. The processor then drives SMIACT active,
saves its register state to SMRAM space, and begins to
execute the SMI handler.
SMI has greater priority than debug exceptions and ex-
ternal interrupts. This means that if more than one of
these conditions occur at an instruction boundary, only
the SMI processing occurs. Subsequent SMI requests
are not acknowledged while the processor is in SMM.
The first SMI request that occurs while the processor is
in SMM is latched, and serviced when the processor
exits SMM with the RSM instruction. Only one SMI signal
is latched by the CPU while it is in SMM. When the CPU
invokes SMM, the CPU core registers are initialized as
indicated in Table 12.
The value in the State Dump base field is not a
32-Kbyte aligned address
A combination of bits in CR0 is illegal: (PG=1 and
PE=0) or (NW=1 and CD=0)
quest to interrupt the HALT state. The SMI handler
can tell the RSM instruction to return control to the
HALT instruction or to return control to the instruc-
tion following the HALT instruction by appropriately
setting the Auto HALT Restart slot. The default op-
eration is to restart the HALT instruction.
I/O access to a powered-down device, the SMI han-
dler can instruct the RSM instruction to re-execute
that I/O instruction by setting the I/O Trap Restart
slot.
SMRAM by setting the SMBASE Relocation slot in
the state save area. The RSM instruction sets
SMBASE in the processor based on the value in the
SMBASE relocation slot. The SMBASE must be
aligned on 32-Kbyte boundaries.
Processor Environment
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