AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 6

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

6
LIST OF FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10 Valid HOLD Assertion During Write-Back ............................................................................................ 26
Figure 11 Closely Coupled Cache Block Diagram ............................................................................................... 27
Figure 12 Snoop Hit Cycle with Write-Back ......................................................................................................... 28
Figure 13 Cycle Reordering with BOFF (Write-Back) .......................................................................................... 29
Figure 14 Write Cycle Reordering Due to Buffering ............................................................................................. 30
Figure 15 Latest Snooping of Copy-Back ............................................................................................................ 32
Figure 16 Burst Write ........................................................................................................................................... 33
Figure 17 Burst Read with BOFF Assertion ......................................................................................................... 33
Figure 18 Burst Write with BOFF Assertion ......................................................................................................... 33
Figure 19 Entering Stop Grant State .................................................................................................................... 36
Figure 20 Stop Clock State Machine .................................................................................................................... 37
Figure 21 Recognition of Inputs when Exiting Stop Grant State .......................................................................... 37
Figure 22 Basic SMI Interrupt Service ................................................................................................................. 39
Figure 23 Basic SMI Hardware Interface .............................................................................................................. 40
Figure 24 SMI Timing for Servicing an I/O Trap ................................................................................................... 40
Figure 25 SMIACT Timing .................................................................................................................................... 41
Figure 26 Redirecting System Memory Address to SMRAM ............................................................................... 41
Figure 27 Transition to and from SMM ................................................................................................................. 43
Figure 28 Auto HALT Restart Register Offset....................................................................................................... 45
Figure 29 I/O Instruction Restart Register Offset ................................................................................................. 46
Figure 30 SMM Base Slot Offset .......................................................................................................................... 46
Figure 31 SRAM Usage ....................................................................................................................................... 47
Figure 32 SMRAM Location ................................................................................................................................. 47
Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode
Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode
Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode
Figure 37 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode
Figure 38 SMM Timing in Systems Using Overlaid Memory Space and Configured in Write-Back Mode ........... 49
Figure 39 CLK Waveforms ................................................................................................................................... 60
Figure 40 Output Valid Delay Timing ................................................................................................................... 60
Figure 41 Maximum Float Delay Timing .............................................................................................................. 61
Figure 42 PCHK Valid Delay Timing .................................................................................................................... 61
Figure 43 Input Setup and Hold Timing ............................................................................................................... 62
Figure 44 RDY and BRDY Input Setup and Hold Timing ..................................................................................... 62
Figure 45 TCK Waveforms ................................................................................................................................... 63
Figure 46 Test Signal Timing Diagram ................................................................................................................. 63
Processor-Induced Line Transitions in Write-Back Mode .................................................................... 20
Snooping State Transitions .................................................................................................................. 20
Typical System Block Diagram for HOLD/HLDA Bus Arbitration ......................................................... 21
External Read ...................................................................................................................................... 22
External Write ...................................................................................................................................... 22
Snoop of On-Chip Cache That Does Not Hit a Line ............................................................................ 23
Snoop of On-Chip Cache That Hits a Non-Modified Line .................................................................... 24
Snoop That Hits a Modified Line (Write-Back) ..................................................................................... 24
Write-Back and Pending Access .......................................................................................................... 25
with Caching Enabled During SMM ...................................................................................................... 48
with Caching Enabled During SMM ...................................................................................................... 48
with Caching Disabled During SMM ..................................................................................................... 48
with Caching Enabled During SMM ...................................................................................................... 49
with Caching Disabled During SMM ..................................................................................................... 49
Enhanced Am486DX Microprocessor Family
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