ISP1562BE STEricsson, ISP1562BE Datasheet - Page 20

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 12.
Table 13.
Legend: * reset value
Table 14.
Legend: * reset value
Table 15.
ISP1562_3
Product data sheet
Bit
23 to 16 BCC[7:0]
15 to 8
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
LT[7:0]
Symbol
CLS[7:0]
Symbol
SCC[7:0]
RLPI[7:0]
CC - Class Code register (address 09h) bit description
CLS - CacheLine Size register (address 0Ch) bit description
LT - Latency Timer register (address 0Dh) bit description
HT - Header Type register (address 0Eh) bit allocation
8.2.1.7 CacheLine Size register
8.2.1.8 Latency Timer register
8.2.1.9 Header Type register
MFD
R
7
1
Access
R/W
Description
Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller.
Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB host controller.
Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI,
which is USB 1.1 specification compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specification compliant.
Access
R/W
The CacheLine Size register is a read and write single-byte register that specifies the
system CacheLine size in units of DWORDs. This register must be implemented by
master devices that can generate the Memory Write and Invalidate command. The value
in this register is also used by master devices to determine whether to use Read, Read
Line or Read Multiple command to access the memory.
Slave devices that want to allow memory bursting using CacheLine-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the CacheLine.
This field must be initialized to logic 0 on activation of RST#.
description of the CacheLine Size register.
This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the
PCI bus master.
The Header Type register identifies the layout of the second part of the predefined header,
beginning at byte 10h in configuration space. It also identifies whether the device contains
multiple functions. For bit allocation, see
R
6
0
Value
00h*
Value
00h*
Table 14
Description
Latency Timer: This byte identifies the latency timer.
R
5
0
Description
CacheLine Size: This byte identifies the system CacheLine size.
Rev. 03 — 14 November 2008
shows the bit description of the Latency Timer register.
R
4
0
Table
HT[6:0]
R
3
0
15.
R
2
0
HS USB PCI host controller
Table 13
R
shows the bit
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R
0
0
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