ISP1562BE STEricsson, ISP1562BE Datasheet - Page 69

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 102. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Content of the base address register + 34h
[1]
Table 103. PERIODICLISTBASE - Periodic Frame List Base Address register bit description
Address: Content of the base address register + 34h
Table 104. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation
Address: Content of the base address register + 38h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 12
11 to 0
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
BA[19:0]
reserved
11.3.6 ASYNCLISTADDR register
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
This 32-bit register contains the address of the next asynchronous queue head to be
executed. If the host controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of
the HCCPARAMS register), the most significant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. For details on the
CTRLDSSEGMENT register, refer to Enhanced Host Controller Interface Specification for
Universal Serial Bus Rev. 1.0 . Bits 4 to 0 of this register always return zeros when read.
The memory structure referenced by the physical memory pointer is assumed as 32 bytes
(cache aligned). For bit allocation, see
Description
Base Address: These bits correspond to memory address signals 31 to 12, respectively.
-
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
BA[3:0]
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 03 — 14 November 2008
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
LPL[26:19]
reserved
BA[19:12]
BA[11:4]
Table
[1]
R/W
R/W
R/W
R/W
R/W
27
19
11
27
104.
0
0
0
3
0
0
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
reserved
HS USB PCI host controller
[1]
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
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