ISP1562BE STEricsson, ISP1562BE Datasheet - Page 28

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 36.
[1]
[2]
Table 37.
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14 to 13 DS[1:0]
12 to 9
8
7 to 2
Address: Value read from address 34h + 4h
Address: Value read from address 34h + 4h
Sticky bit, if the function supports PME# from D3
function does not support PME# from D3
The reserved bits should always be written with the reset value.
Symbol
PMES
D_S
[3:0]
PMEE
reserved
PMCSR - Power Management Control/Status register bit allocation
PMCSR - Power Management Control/Status register bit description
8.2.3.4 PMCSR register
PMES
R/W
R/W
X
15
7
0
[1]
Description
PME Status: This bit is set when the function normally asserts the PME# signal independent of the
state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting
PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not
support the PME# generation from D3
then this bit is sticky and must be explicitly cleared by the operating system each time the operating
system is initially loaded.
Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of the
Data register. The value and meaning of this field vary, depending on which data value is selected by
the D_S field. This field is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this field
must return 00b when PMCSR is read.
Data Select: This four-bit field selects the data that is reported through the Data register and the D_S
field. This field is a required component of the Data register (offset 7) and must be implemented, if the
Data register is implemented. If the Data register is not implemented, this field must return 00b when
PMCSR is read.
PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is
disabled. This bit defaults to logic 0, if the function does not support the PME# generation from D3
If the function supports PME# from D3
operating system each time the operating system is initially loaded.
-
The Power Management Control/Status (PMCSR) register is a 2-byte register used to
manage the power management state of the PCI function, as well as to allow and monitor
Power Management Events (PMEs). The bit allocation of the register is given in
R/W
14
R
0
6
0
DS[1:0]
cold
.
R/W
13
R
0
5
0
cold
Rev. 03 — 14 November 2008
reserved
, then X is indeterminate at the time of initial operating system boot; X is 0 if the
[2]
R/W
R/W
cold
12
cold
0
4
0
. If the function supports the PME# generation from D3
, then this bit is sticky and must be explicitly cleared by the
R/W
R/W
11
0
3
0
D_S[3:0]
R/W
R/W
10
0
2
0
HS USB PCI host controller
R/W
R/W
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
PS[1:0]
Table
PMEE
R/W
R/W
X
8
0
0
27 of 93
[1]
cold
cold
36.
,
.