ISP1562BE STEricsson, ISP1562BE Datasheet - Page 67

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 98.
Address: Content of the base address register + 28h
Table 99.
Address: Content of the base address register + 2Ch
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
reserved
IAAE
HSEE
FLRE
PCIE
USB
ERRINTE
USBINTE
USBINTR - USB Interrupt Enable register bit description
FRINDEX - Frame Index register bit allocation
11.3.4 FRINDEX register
R/W
R/W
31
7
0
0
reserved
Description
-
Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS
register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing bit IAA.
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.
Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR.
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the
host controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD.
USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set,
the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged
by software clearing bit USBERRINT.
USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the host
controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit USBINT.
The Frame Index (FRINDEX) register is used by the host controller to index into the
periodic frame list. The register updates every 125 s, once each microframe. Bits N to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register
must be written as a DWORD. Byte writes produce undefined results. This register cannot
be written unless the host controller is in the halted state, as indicated by HCH (bit 12 in
the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is
set produces undefined results. Writes to this register also affect the SOF value.
The bit allocation is given in
[1]
R/W
R/W
30
6
0
0
IAAE
R/W
R/W
29
5
0
0
Rev. 03 — 14 November 2008
Table
HSEE
R/W
R/W
28
4
0
0
99.
reserved
[1]
FLRE
R/W
R/W
27
3
0
0
PCIE
R/W
R/W
26
2
0
0
HS USB PCI host controller
USBERR
INTE
R/W
R/W
25
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1562
USBINTE
R/W
R/W
24
0
0
0
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