ISP1562BE STEricsson, ISP1562BE Datasheet - Page 24

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 26.
Legend: * reset value
Table 27.
[1]
Table 28.
ISP1562_3
Product data sheet
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
7 to 6
5 to 0
The reserved bits should always be written with the reset value.
Symbol
reserved
FLADJ[5:0]
Symbol
SBRN[7:0] R
SBRN - Serial Bus Release Number register (address 60h) bit description
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
FLADJ - Frame Length Adjustment register (address 61h) bit description
8.2.2.1 SBRN register
8.2.2.2 FLADJ register
8.2.2 Enhanced host controller-specific PCI registers
R/W
7
0
reserved
Access
In addition to the PCI configuration header registers, EHCI needs some additional PCI
configuration space registers to indicate the serial bus release number, downstream port
wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).
The EHCI-specific PCI registers are given in
Table 25.
The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit
description is given in
specification with which this USB host controller module is compliant.
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in
Description
-
Frame Length Timing Value: Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a
SOF microframe length, is equal to 59488 + value in this field. The default value is decimal 32
(20h), which gives a SOF cycle time of 60000; see
Offset
60h
61h
62h to 63h
[1]
R/W
Value
20h*
6
0
Table
EHCI-specific PCI registers
27.
Description
Serial Bus Specification Release Number: This register value is to identify
Universal Serial Bus Specification Rev. 2.0 . All other combinations are reserved.
R/W
5
1
Rev. 03 — 14 November 2008
Table
Register
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Port Wake Capability (PORTWAKECAP)
26. This register contains the release number of the USB
R/W
4
0
R/W
Table
3
0
Table
FLADJ[5:0]
25.
29.
R/W
2
0
HS USB PCI host controller
R/W
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
R/W
0
0
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