TE28F160S375 Intel, TE28F160S375 Datasheet - Page 12

• Manufacturer Part Number: TE28F160S375
• Manufacturer: Intel

Specifications of TE28F160S375

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 75ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S3, 28F320S3
3.0
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1
Block information, query information, identifier
codes and Status Registers can be read
independent of the V
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE
active to obtain data at the outputs. CE
CE
when both are active, enable the selected
memory device. OE# is the data output (DQ
DQ
memory data onto the I/O bus. WE# must be at
V
a read cycle.
3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3
CE
the device in standby mode, substantially
reducing device power consumption. DQ
(or DQ
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit
functioning and consuming active power until the
operation completes.
12
IH
1
0
15
and RP# must be at V
# are the device selection controls, and,
# or CE
) control: When active it drives the selected
deep
0
– DQ
BUS OPERATION
Read
Output Disable
Standby
configuration,
1
7
# at a logic-high level (V
power-down
in x8 mode) outputs are placed in
0
#, CE
PP
1
# and OE# must be driven
voltage.
the
IH
. Figure 17 illustrates
mode,
device
IH
), the device
the
0
–DQ
IH
continues
) places
0
0
device
–DQ
# and
15
are
0
15
–
3.4
RP# at V
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the Status
Register is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data
programming or partially altered after an erase or
lock-bit configuration. Time t
RP# goes to logic-high (V
command can be written.
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash
provide status information when accessed during
block
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
ADVANCE INFORMATION
memory.
may
Flash
IL
erase,
Deep Power-Down
Read Query Operation
initiates the deep power-down mode.
be
memories
Automated
programming,
PLPH
partially
. Time t
PHWL
allow
IH
) before another
corrupted
flash
PHQV
is required after
proper
or
is required
memories
lock-bit
CPU
after