TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 6

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
Each TU/VT Terminate block (A and B side) performs pointer processing based on the location of the V1 and
V2 bytes. The pointer bytes are monitored for loss of pointer, TU AIS indication, and NDF. The pointer tracking
process is based on the latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer incre-
ments and decrements are also counted, and the SS-bits are monitored for the correct value. This block also
monitors the various alarms found in the V5 and K4 (formerly known as Z7) bytes, including signal label mis-
match detection, unequipped status detection, BIP-2 parity error detection and error counter, FEBE counter,
and the three RDI indications. The Quad E1 Mapper performs a 16-byte J2 trail trace comparison on the chan-
nels selected. For 64-byte messages, the bytes are stored in a memory map segment for a microprocessor
read cycle. The device also provides the TU tandem connection feature and performs the 16-byte message
comparison for the N2 (formerly known as Z6) byte message.
A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in
the Destuff block using majority logic rules for the three sets of three justification control bits to determine if the
two S-bits are data bits or frequency justification bits.
The Desync block removes the effects on the E1 output of systemic jitter that might occur because of signal
mappings and pointer movements in the network. The Desync block contains two parts, a pointer leak buffer,
and a E1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can
adjust the effect over time. The E1 Loop Buffer consists of a digital loop filter, which is designed to track the fre-
quency of the received E1 signal and to remove both transmission and stuffing jitter.
An option for each port provides either NRZ data, or an HDB3-encoded positive and negative rail signal for the
E1 interface. Receive data (towards the E1 line), for all four channels, can be clocked out on either rising or
falling edges of the clock. In addition, control bits are provided for forcing the data and clock signals to a high
impedance state (tristate). A control lead is provided for forcing the output leads to the 0 state.
In the add direction, the Quad E1 Mapper accepts clock and either NRZ data or HDB3-encoded positive and
negative rail signals. Data, for all four channels, can be clocked in on either the falling or rising edge of the
clock. In the NRZ mode, an external loss of clock indication input signal can be provided. For the rail signal,
coding violations are counted, and there is monitoring for loss of signal. An E1AIS detector is also provided.
The data signal is written into a FIFO in one of the eight Stuff/Sync blocks. Threshold modulation is used for
the frequency justification process. Timing information from the drop bus or add bus is used to read the FIFO
and perform the TU/VT justification process. This block permits tracking of an incoming E1 signal having an
average frequency offset as high as 120 ppm, and up to 1.5 UI of peak-to-peak jitter. Since the Quad E1 Map-
per supports a ring architecture, two sets of blocks are provided for each port. The TU/VT selection is the same
for both blocks. A control bit, and transmit line alarms, can generate an E1AIS.
The eight TU/VT Build blocks format the TU/VT into a STS-1, STS-3 or STM-1 structure for the asynchronous
2048 kbit/s signals, as shown in 2. The pointer value carried in the V1 and V2 bytes is transmitted with a fixed
value of 105. Transmit access is provided for the 8 overhead communications channel bits (O-bits) via the
microprocessor. The microprocessor also writes the signal label, and the value of the J2 message, either as a
16-byte or a 64-byte message. The Quad E1 Mapper provides the TU tandem connection feature for the TU,
including the transmission of the 16-byte message and the various alarms associated with the tandem connec-
tion feature. The device provides three-bit RDI using the V5 and K4 (Z7) bytes. Local alarms, or the micropro-
cessor, can generate the remote payload, server, or connectivity defect indications. The Far End Block Error
(FEBE) is inserted from the BIP-2 errors detected on the receive side, and BIP-2 parity is generated for the V5
byte. Control bits are provided for generating unequipped status, generating TU/VT AIS, and inserting FEBE
and BIP-2 errors. The ability to generate Null Pointer Indicators (NPIs) is also provided for the STM-1 VC-4 for-
mat.
The A Transmit block is identical to the B Transmit block. The interface between an add bus and a Transmit
block consists of three input leads and eleven output leads, when the add bus timing mode is selected. The
input leads are a byte clock, a C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, a
parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The Add C1J1V1 signal is
used in conjunction with the Add SPE signal to determine the location of the various pulses. An option is pro-
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DATA SHEET
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