TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet
TMXF846221BL-3-DB
Specifications of TMXF846221BL-3-DB
Related parts for TMXF846221BL-3-DB
TMXF846221BL-3-DB Summary of contents
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TMXF84622 Ultramapper ™ 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 1 Introduction The last issue of this data sheet was July 12, 2004 - Revision 9. A change history is included in on page 72. Red change bars have been installed on ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Contents 1 Introduction ........................................................................................................................................................................1 2 Pin Information ...................................................................................................................................................................6 2.1 Ball Diagram ................................................................................................................................................................6 2.2 Package Pin Assignments ...........................................................................................................................................7 2.3 Pin Matrix ...................................................................................................................................................................15 2.4 Pin Types ...................................................................................................................................................................17 2.5 Pin Definitions ............................................................................................................................................................18 3 Operating Conditions and ...
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Hardware Design Guide, Revision 10 April 5, 2005 Tables Table 2-1. Package Pin Assignments in Signal Name Order .................................................................................................7 Table 2-2. Package Pin Matrix .............................................................................................................................................15 Table 2-3. Pin Types ............................................................................................................................................................17 Table 2-4. TMUX Block, High-Speed Interface I/O...............................................................................................................18 Table 2-5. TMUX ...
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Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Tables Table 5-15. Shared Low-Speed Line Timing Output Specifications .....................................................................................51 Table 5-16. CHIRXGCLK and CHITXGCLK Timing Specifications......................................................................................51 Table 5-17. CHI Interface Timing Specifications ..................................................................................................................52 Table 5-18. PSB Inputs Specifications .................................................................................................................................54 Table 5-19. PSB Output Specifications ...
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Hardware Design Guide, Revision 10 April 5, 2005 Figures Figure 1-1. Ultramapper Block Diagram and High-Level Interface Definition.........................................................................1 Figure 2-1. Ultramapper Package Diagram (Top View) .........................................................................................................6 Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................41 Figure 5-2. TMUX LVDS Clock and Data ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 2 Pin Information 2.1 Ball Diagram The TMXF84622 Ultramapper is housed in a 700-pin plastic ball grid array. Figure 1-1 shows the ball assignment viewed from the top of the package. The pins ...
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Hardware Design Guide, Revision 10 April 5, 2005 2.2 Package Pin Assignments Table 2-1. Package Pin Assignments in Signal Name Order Signal Name ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name CHITXDATA[21] CHITXDATA[22] CHITXDATA[23] CHITXDATA[24] CHITXDATA[25] CHITXDATA[26] CHITXDATA[27] CHITXDATA[28] CHITXDATA[29] CHITXDATA[30] CHITXDATA[31] CHITXDATA[32] CHITXDATA[33] CHITXDATA[34] CHITXDATA[35] CHITXDATA[36] CHITXDATA[37] CHITXDATA[38] CHITXDATA[39] CHITXDATA[40] CHITXDATA[41] ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name DS3XCLK DSN DTN E1XCLK E2AISCLK E3XCLK ECSEL ETOGGLE EXDNUP HP_INTN IC3STATEN IDDQ LINERXCLK[1] LINERXCLK[2] LINERXCLK[3] LINERXCLK[4] LINERXCLK[5] LINERXCLK[6] LINERXCLK[7] LINERXCLK[8] ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name LINETXCLK[19] LINETXCLK[20] LINETXCLK[21] LINETXCLK[22] LINETXCLK[23] LINETXCLK[24] LINETXCLK[25] LINETXCLK[26] LINETXCLK[27] LINETXCLK[28] LINETXCLK[29] LINETXCLK[30] LINETXDATA[1] LINETXDATA[2] LINETXDATA[3] LINETXDATA[4] LINETXDATA[5] LINETXDATA[6] LINETXDATA[7] LINETXDATA[8] LINETXDATA[9] ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name RHSCN RHSCP RHSDN RHSDP RHSFSYNCN RLSCLK RLSDATAN[1] RLSDATAN[2] RLSDATAN[3] RLSDATAP[1] RLSDATAP[2] RLSDATAP[3] RPOACCLK RPOACDATA RPOACSYNC RPSCN RPSCP RPSDN RPSDP RSTN ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-1. Package Pin Assignments in Signal Name Order (continued) Signal Name ...
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Hardware Design Guide, Revision 10 March 7, 2005 2.3 Pin Matrix Table 2-2. Package Pin Matrix LINERXDATA LINERXDATA[30] SS DD33 [27] LINERXCLK DD33 SS DD33 [29] C CSN V ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-2. Package Pin Matrix (continued LINERXCLK[1] V DS3XCLK SS SSA_E3PLL LOPO- B LINERXDATA[3] LINERXDATA[1] V DD15A_E3PLL HDATAOUT LOPO- C LINERXCLK[2] — V DD15A_DS3PLL HDATAIN D V ...
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Hardware Design Guide, Revision 10 April 5, 2005 2.4 Pin Types Table 2-3 describes each type of input, output, and I/O pin used in the Ultramapper. Table 2-3. Pin Types Type Label I LVCMOS Input, LVTTL Switching Thresholds ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 2.5 Pin Definitions This section describes the function of each of the device pins. All LVDS input buffers have built-in 100 Ω terminating resistor with a center tap pin available for external capacitor ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-6. TMUX Block, Clock, and Sync I/O Pin Symbol Type AP6 THSCP L Transmit High-Speed Clock. 622 MHz/155 MHz input clock for transmit IN 622/155 Mbits/s data. Also used as a ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-7. STS Cross Connect (STSXC) Block, STS-3/STM-1 Mate Interconnect Pin Symbol AP17, AP15, RLSDATAP[3:1] AP13 AP18, AP16, RLSDATAN[3:1] AP14 AN17, AN15, TLSDATAP[3:1] AN13 AN18, AN16, TLSDATAN[3:1] AN14 AJ13 CTAPTL Table 2-8. Synchronous ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-9. Multirate Cross Connect (MRXC) Block, TOAC Input and Output Channels Pin Symbol AM17 RTOACCLK AJ17 RTOACDATA AM18 RTOACSYNC AL18 TTOACCLK AP19 TTOACDATA AK18 TTOACSYNC Table 2-10. Multirate Cross Connect (MRXC) ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-11. DS3/E3/STS-1 Out Pin Symbol AF2, AD5, DS3POSDATAOUT[6:1] AE1, AD1, AA5, AB2 AF3, AC6, DS3NEGDATAOUT[6:1] AF1, AD2, AA6, AB1 AD6, AG1, DS3DATAOUTCLK[6:1] AD3, AC3, AC2, Y6 AH1, AE2, DS3RXCLKOUT[6:1] AC5, AB6, AC1, ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-13. NSMI/STS-1 In Pin Symbol AP28, AK24, NSMIRXDATA[3:1] AK23 AJ24, AP27, NSMIRXCLK[3:1] AP26 AN27, AN26, NSMIRXSYNC[3:1] AN25 AM27, AM26, RXDATAEN[3:1] AJ23 * The transmit path is toward the high-speed fiber output ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-14. NSMI/STS-1 Out Pin Symbol AP31, AN28, NSMITXDATA[3:1] AJ25 AM29, AP30, NSMITXCLK[3:1] AP29 AN30, AN29, NSMITXSYNC[3:1] AK26 AM30, AK27, TXDATAEN[3:1] AJ26 * The transmit path is toward the high-speed fiber output and ...
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Hardware Design Guide, Revision 10 April 5, 2005 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., LINERXDATA, on the transmit path are labeled receive. Low-speed outputs, e. ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-17. TDM Concentration Highway (CHI) In Pin Symbol J32, J33, H34, CHIRXDATA[42:1] L30, M29, K33, J34, M30, L32, K34, L33, N29, M32, L34, M33, P29, M34, P30, N33, P32, N34, R29, P33, ...
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Hardware Design Guide, Revision 10 April 5, 2005 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e. ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-19. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync Pin Symbol Type Y32 CHIRXGTCLK I pd W29 CHIRXGCLK I pd Y33 CHIRXGFS I pd AA34 CHITXGFS I pd Y30 CHITXGCLK ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-20. Reference Clocks Pin Symbol Type R1 DS2AISCLK E2AISCLK I pd AP21 E1XCLK I pd AK20 DS1XCLK I pd A21 DS3XCLK I pd F18 E3XCLK I pd Table ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-21. Low-Order Path Overhead Access, Transmit Direction Pin Symbol Type A22 LOPOHVALIDIN I pd Table 2-22. Low-Order Path Overhead Access, Receive Direction Pin Symbol Type F20 LOPOHCLKOUT B21 LOPOHDATAOUT E20 LOPOHVALIDOUT Table ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-24. Microprocessor Interface Pin Symbol F5 MPCLK F6 MPMODE C1 CSN D2 ADSN H6 RWN E3 DSN K2, M6, L5, ADDR[20:0] H1, J2, J3, G1, L6, H2, H3, K6, F1, J5, ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-25. Boundary Scan (IEEE Pin Symbol AN22 TCK AK21 TDI AP23 TMS AJ21 TRST AN23 TDO Table 2-26. General-Purpose Interface Pin Symbol AP22 RSTN AM21 PMRST AP24 IC3STATEN AM23 SCK1 AJ22 SCK2 ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 2-28. Analog Power and Ground Signals Pin Symbol AK12 V SSA_CDR1 AJ12 V SSA_CDR2 AJ11 V SSA_X4PLL AL34 V SSA_SFPLL F19 V SSA_DS3PLL A20 V SSA_E3PLL AK11 V DD15A_CDR1 AJ10 V ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 2-29. Digital Power and Ground Signals AA7, AA16, AA17, AA18, AA19, AA28, AB7, AB16, AB17, AB18, AB19, AB28, AC7, AC28, AD7, AD28, AE7, AE28, AF7, AF28, AH9, AH10, AH11, AH12, AH13, AH14, ...
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Hardware Design Guide, Revision 10 April 5, 2005 3 Operating Conditions and Reliability 3.1 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 3.4 Thermal Parameters (Definitions and Values) System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of ...
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Hardware Design Guide, Revision 10 April 5, 2005 3.5 Reliability Product reliability can be calculated as the probability that the product will perform under normal operating conditions for a set period of time. Factors influencing the reliability of a product ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 3.7 Power Consumption The power consumption of the device is application dependent since it is not possible to use all the device features simul- taneously. The nominal measured values for power per block ...
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Hardware Design Guide, Revision 10 April 5, 2005 4 Electrical Characteristics 4.1 LVCMOS Interface Specifications Table 4-1. LVCMOS Input Specifications Parameter Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance * Excludes current due to pull-up or pull-down resistors. Table ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 4.2 LVDS Interface Characteristics 3.3 V ± –40 °C to +125 °C junction temperature Table 4-4. LVDS Interface dc Characteristics Parameter Input Voltage Range: High ( ...
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Hardware Design Guide, Revision 10 April 5, 2005 5 Timing 5.1 TMUX High-Speed Interface Timing 80% 20% 50% RHSCP/N RHSDP/N 50% 50% THSCOP/N THSDP/N Table 5-1. High-Speed Interface Inputs Specifications Name * RHSDP/N (622 MHz) Asynchronous * RHSDP/N (155 MHz) ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 5-2. Protection Link Inputs Specifications Name Reference * RPSDP/N (622 MHz) Asynchronous * RPSDP/N (155 MHz) Asynchronous RPSDP/N (155 MHz) * Input serial data stream should have minimum eye opening of 0.4 ...
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Hardware Design Guide, Revision 10 April 5, 2005 When MPU_MASTER_SLAVE = 0, then THSSYNC (supplied from an external source) can be according to Figure 5-4. 125 µs STS FIRST FRAME 50 ns STS-12 J0 125 µs FIRST ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.3 STS-3/STM-1 Mate Interconnect Timing 80% 20% 50% CLOCK TLSDATAP/N 50% 50% CLOCK RLSDATAP/N Figure 5-8. STS-3/STM-1 Mate Clock and Data Timing Table 5-5. STS-3/STM-1 Mate Interconnect Input Specifications Name Reference TLSDATAP/N[3:1] Asynchronous ...
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Hardware Design Guide, Revision 10 April 5, 2005 5.4 TOAC, POAC, and LOPOH Timing The relationships between data, clock, and sync signals are specific to the TOAC and POAC operation mode selected. This is explained in detail in the TOAC/POAC ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.5 DS3/E3/STS-1 Timing Figure 5-11 shows a simplified representation of the DS3/E3/STS-1 I/O. Q CLK DS3DATAINCLK DS3POSDATAIN DS3NEGDATAIN Figure 5-11. DS3/E3 Interface Diagram in M13/E13 Block Table 5-9. DS3/E3 Inputs Specifications Name Reference ...
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Hardware Design Guide, Revision 10 April 5, 2005 5.6 NSMI Timing NSMIRXCLK NSMITXCLK t SU NSMIRXDATA t PD NSMITXDATA Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode SONET Frame (for info only) NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 DS3 frame X1 (for info only) NSMI_TXCLK 44.736 MHz NSMI_TXDATAEN NSMI_TXDATA NSMI_TXSYNC DS3 Frame X1 NSMI_RXCLK 44.736 MHz Output NSMI_RXDATAEN NSMI_RXDATA NSMI_RXSYNC Notes: Clock from M13 is at 44.736 MHz rate and is ...
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Hardware Design Guide, Revision 10 April 5, 2005 E3 frame (for info only) NSMI_TXCLK (51.84 MHz output) NSMI_TXDATAEN (output) NSMI_TXDATA (output) NSMI_TXSYNC (output) E3 frame (For info only) NSMI_RXCLK (51.84 MHz output) NSMI_RXDATAEN (output) NSMI_RXDATA (Input) NSMI_RXSYNC (output) Notes: Clock ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 NSMITXCLK NSMITXDATA MSB START NSMITXSYNC NSMITXCLK 51.84MHz NSMITXDATA DATA 1,1 DATA 2,1 DATA Link#,Byte# NSMITXSYNC Binary Value 01100000 01010000 Link Number Provisionable 1:28 or 0:27 for DS1 FSYNC High signifies 1 Start goes ...
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Hardware Design Guide, Revision 10 April 5, 2005 5.7 Shared Low-Speed Line Timing LINERXCLK LINETXCLK t SU LINERXDATA t PD LINETXDATA Note: Single rail shown. Figure 5-18. Shared Low-Speed Line Clock and Data Timing Table 5-14. Shared Low-Speed Line Timing ...
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... CHITXGCLK CHIRXDATA CHITXDATA Note: This figure assumes TMXF846221BL-2 is programmed to sample the frame sync signal on the rising edge of the bit clock. Table 5-17. CHI Interface Timing Specifications Parameter t Frame Sync Setup Time to Active CHI Clock Edge 5 t Frame Sync Hold Time from Active CHI Clock Edge ...
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Hardware Design Guide, Revision 10 April 5, 2005 CHIRXGFS CHIRXGCLK w/ 0 offset w/ ½ bit offset w/ bit offset = offset = 1, bit offset = offset = 255, bit offset = 7½ ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 5.9 Parallel System Bus (PSB) Timing CHIRXGCLK CHITXGCLK CHIRXGFS CHITXGFS CHIRXDATA t PD CHITXDATA Table 5-18. PSB Inputs Specifications Name CHIRXDATA[16:1] (PSB mode) CHIRXGFS (PSB ...
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Hardware Design Guide, Revision 10 April 5, 2005 6 Reference Clocks Table 6-1. High-Speed Interface Input Clocks Specifications Clock Name Period Frequency Accuracy (ns) RHSCP/N 6.43 155.52 MHz THSCP/N 6.43 155.52 MHz THSCP/N 1.6 622.08 MHz Table 6-2. Protection Link ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 6-5. M13/E13 Input Clocks Specifications Clock Name Period Frequency (ns) DS2AISCLK 158.42 6.312 MHz E2AISCLK 118.37 8.448 MHz Table 6-6. DS3/E3 DJA Input Clocks Specifications Clock Name Period Frequency (ns) DS3XCLK 22.35 ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 6-11. PSB Input Clocks Specifications Clock Name CHIRXGCLK (PSB mode) CHITXGCLK (PSB mode) Table 6-12. High-Speed Interface Output Clocks Specifications Clock Name THSCOP/N THSCOP/N Table 6-13. Protection Link Output Clocks Specifications ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 6-16. POAC Output Clocks Specifications Clock Name RPOACCLK (TMUX) RPOACCLK (STS1LT) RPOACCLK (SPEMPR) TPOACCLK (TMUX) TPOACCLK (STS1LT) TPOACCLK (SPEMPR) Table 6-17. DS3/E3/STS-1 Output Clocks Specifications Clock Name DS3RXCLKOUT [6:1](DS3) DS3RXCLKOUT [6:1](E3) DS3RXCLKOUT ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 6-21. Shared Low-Speed Receive Line Input/Output Clocks Specifications (continued) Clock Name Period (ns) Frequency LINERXCLK (E23) LINERXCLK (DJA; DS1) LINERXCLK (DJA; E1) LINERXCLK (TPG; DS1) LINERXCLK (TPG; E1) Table 6-22. Shared ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 7 Microprocessor Interface Timing Note: To allow proper operation of the microprocessor interface upon device/board bring up, the recommended powerup sequence (listed in Section avoid potential bus contention issues, the IC3STATEN pin should ...
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Hardware Design Guide, Revision 10 April 5, 2005 Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications Symbol Parameter MPCLK MPCLK 16 MHz Min—66 t ADSN, RWN, DATA (write) Valid to MPCLK WS t MPCLK to ADDR, RWN, DATA, CSN (write) ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 7.2 Synchronous Read Mode MPCLK ADDR[20:0] t CSN t ADSNSU ADSN RWN HIGH Z DTN DATA[15:0] (OUTPUT) Notes: MPCLK Input clock to Ultramapper MPU block. ADDR [20:0] The address will be available throughout ...
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Hardware Design Guide, Revision 10 April 5, 2005 7.3 Asynchronous Write Mode The asynchronous microprocessor interface mode is selected when MPMODE (pin F6 Interface timing for the asyn- chronous mode write cycle is given in Figure 7-3 and ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol Parameter MPCLK MPCLK 16 MHz Min—66 MHz Max Frequency t CSN Fall Setup and Hold to DSN Fall CSFDSF t CSN Rise to ADDR ...
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Hardware Design Guide, Revision 10 April 5, 2005 7.4 Asynchronous Read Mode ADDR[20:0] CSN ADSN DSN RWN DTN HIGH Z DATA[15:0] Notes: ADDR [20:0] Address is asynchronously passed from the host bus to the internal bus. The address will be ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications Symbol Parameter MPCLK MPCLK 16 MHz Min—66 MHz Max Frequency t CSN Fall Setup and Hold to DSN Fall CSFDSF t CSN Rise to ADDR ...
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Hardware Design Guide, Revision 10 April 5, 2005 8 Other Timing This interface may be used as either synchronous or asynchronous mode. Table 8-1. General-Purpose Inputs Specifications Name RSTN PMRST TDI and TMS Table 8-2. Miscellaneous Output Specifications Name RHSFSYNCN ...
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TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 10 700-Pin PBGAM1T Diagrams Figure 10-1. 700-Pin PBGAM1T Hardware Design Guide, Revision 10 Physical Dimension April 5, 2005 Agere Systems Inc. ...
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Hardware Design Guide, Revision 10 April 5, 2005 Figure 10-2. Bottom View of 700-Pin Agere Systems Inc. 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 PBGAM1T Balls Location TMXF84622 Ultramapper 69 ...
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... TMXF84622 Ultramapper 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 11 Ordering Information Table 11-1. Ordering Information Device TMXF846221BL-21 TMXF846221BL-3 L-TMXF846221BL-3* * Pb-free/RoHS 70 70 Hardware Design Guide, Revision 10 Package 700-pin PBGAM1T 700-pin PBGAM1T 700-pin PBGAM1T April 5, 2005 Comcode 700054129 700052305 700077978 Agere Systems Inc. ...
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Hardware Design Guide, Revision 10 April 5, 2005 12 Glossary AIS Alarm indication signal AMI Alternate mark inversion APS Automatic protection switch ASM Associated signaling mode BER Bit error rate BLSR Bidirectional line switched ring BOM Bit-oriented message BPV Bipolar ...
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Serializer/Deserializer (SERDES) Serial TMXF84622 Ultramapper Serial Interface for the MACROs 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0 13 Change History 13.1 Changes to this Document Since Revision 9 On page 31, deleted STS1LT from the description. On page 39, added two rows ...