TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet - Page 18

• Manufacturer Part Number: TMXF846221BL-3-DB
• Manufacturer: LSI

Specifications of TMXF846221BL-3-DB

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

TMXF84622 Ultramapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0
2.5 Pin Definitions
This section describes the function of each of the device pins. All LVDS input buffers have built-in 100 Ω terminating
resistor with a center tap pin available for external capacitor connection. All unused LVDS inputs may be left unconnected.
Pin functionality is descriptive information. The actual functionality is dependent upon the device configuration via the
registers.
Table 2-4. TMUX Block, High-Speed Interface I/O
Table 2-5. TMUX Block, Protection Link I/O
18
18
* Optional: selected by MPU/top-level register UMPR_LVDS_REF_SEL. External reference voltage can be sourced from a low-impedance resistor
AN10
AN11
AP10
(less than 1 kΩ) divider circuit decoupled with a 0.1 µF capacitor. Please refer to
tional information.
AP11
AN21
AM8
AM9
AP3,
AM5
AM6
AK9
AP8
AP9
AN4
AN5
AN7
AN8
AK8
AP4
AP5
AK6
AJ8
AJ6
Pin
Pin
THSCON
CTAPRP
THSCOP
CTAPRH
LOSEXT
Symbol
RPSDP
RPSDN
RPSCP
RPSCN
Symbol
TPSDP
TPSDN
TPSCP
TPSCN
RHSDP
RHSDN
RHSCP
RHSCN
THSDP
THSDN
RESLO
REF10
REF14
RESHI,
*
*
Type
L
L
Type
L
L
I pu External Loss of Signal Input. Active level is programmable by register
L
L
L
L
OUT
OUT
OUT
OUT
—
—
—
IN
IN
I
I
IN
IN
Receive Protection High-Speed Data. 622/155 Mbits/s protection input data. Also input to
internal protection CDR. CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s mode,
the internal CDR must be used.
Receive Protection High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if protec-
tion CDR is bypassed. Not used in 622 Mbits/s mode.
Center Tap RP. LVDS buffer terminator center tap for RPSDP/N and RPSCP/N. An optional
0.1 µF capacitor, connected between the CTAP pin and ground, will improve the common-
mode rejection of the LVDS input buffers.
Transmit Protection High-Speed Data. 622/155 Mbits/s protection output data.
Transmit Protection High-Speed Clock. 622/155 MHz transmit output clock associated with
TPSDP/N.
Receive High-Speed Data. 622/155 Mbits/s input data. Also, input to internal clock and data
recovery (CDR). CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s mode, the
internal CDR must be used.
Receive High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if CDR is bypassed.
Not used in 622 Mbits/s mode.
Center Tap RH. LVDS buffer terminator center tap for RHSDP/N and RHSCP/N. An optional
0.1 µF capacitor, connected between CTAP pin and ground, will improve the common-mode
rejection of the LVDS input buffers.
TMUX_LOSEXT_LEVEL. Default to active-low. This pin can be part of the high-priority
interrupt when active. Usually connected to optical transceiver to indicate loss of signal.
Transmit High-Speed Data. 622/155 Mbits/s output data. The frame location in slave mode
is determined by THSSYNC and transmit high-speed control parameter register
(TMUX_TFRAMEOFFSETA). In master mode the frame timing is arbitrary.
Transmit High-Speed Clock Output. 622/155 MHz transmit output clock associated with
THSDP/N.
Resistor. A 100 Ω, 1% resistor is required between RESHI and RESLO pins as a reference
for the LVDS input buffer termination.
Reference 1.0 V. External 1 V reference voltage pin. (Optional).
Reference 1.4 V. External 1.4 V reference voltage pin. (Optional).
Table 4-4 LVDS Interface dc Characteristics, on page 40
Name/Description
Name/Description
Hardware Design Guide, Revision 10
Agere Systems Inc.
April 5, 2005
for addi-