TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet - Page 56

• Manufacturer Part Number: TMXF846221BL-3-DB
• Manufacturer: LSI

Specifications of TMXF846221BL-3-DB

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

TMXF84622 Ultramapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0
Table 6-5. M13/E13 Input Clocks Specifications
Table 6-6. DS3/E3 DJA Input Clocks Specifications
Table 6-7. LOPOH Input Clock Specifications
Table 6-8. Microprocessor Interface Input Clocks Specifications
Table 6-9. Framer PLL Input Clocks Specifications
Table 6-10. CHI Input Clocks Specifications
56
56
LOPOHCLKIN
MPCLK (min)
MPCLK (max)
DS2AISCLK
E2AISCLK
DS3XCLK
E3XCLK
CLKIN_PLL
CHIRXGTCLK (DS1 mode) 647.66
CHIRXGTCLK (E1 mode)
CHIRXGCLK (CHI mode)
CHIRXGCLK (CHI mode)
CHIRXGCLK (CHI mode)
CHIRXGCLK (CHI mode)
CHITXGCLK (CHI mode)
CHITXGCLK (CHI mode)
CHITXGCLK (CHI mode)
CHITXGCLK (CHI mode)
* The following applies to the synchronous microprocessor mode (MPMODE pin = 1): If DTN is used, then the maximum frequency for MPCLK is
determined by the processor’s setup specification for DTN. MPU maximum bus operating frequency = 1/(MPU DTN setup time + tDTNVPD). For
example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detection.
Clock Name
Clock Name
Clock Name
Clock Name
Clock Name
Clock Name
*
Period
Period
Period
Period
158.42
118.37
22.35
29.09
51.44
62.5
15.0
(ns)
(ns)
(ns)
(ns)
Frequency
44.736 MHz
34.368 MHz
Frequency
19.44 MHz
66.67
Frequency
Frequency
8.448 MHz
Period
Period
6.312 MHz
488.28
488.28 2.048 MHz
244.14 4.096 MHz
122.07 8.192 MHz
61.035 16.384 MHz
488.28 2.048 MHz
244.14 4.096 MHz
122.07 8.192 MHz
61.035 16.384 MHz
16 MHz
19.2
(ns)
(ns)
MHz
Frequency Accuracy
Frequency Accuracy
51.84 MHz
1.544 MHz
2.048 MHz
Accuracy
Accuracy
Accuracy
Accuracy
(ppm)
(ppm)
(ppm)
(ppm)
—
—
—
20
20
30
30
(ppm)
(ppm)
50
50
50
50
50
50
50
50
20
32
50
0.01 UIp-p or 0.22 nsp-p
0.01 UIp-p or 0.29 nsp-p
(100 Hz—800 kHz)
(10 Hz—400 kHz)
GR-499 and G.823
Jitter
Jitter
Jitter
Jitter
—
—
—
—
—
GR-499
G.823
Jitter
Jitter
—
—
—
—
—
—
—
—
Hardware Design Guide, Revision 10
Rise
(ns)
Rise
Rise
Rise
Rise
Rise
(ns)
3.5
3.5
(ns)
(ns)
(ns)
(ns)
10
10
—
10
10
10
10
10
10
10
10
5
8
4
4
5
(ns)
Fall
(ns)
(ns)
Fall
(ns)
3.5
3.5
Fall
(ns)
(ns)
Fall
Fall
Fall
10
10
—
10
10
10
10
10
10
10
10
8
5
5
4
4
Min/Max
Min/Max
Min/Max
Min/
Max
Max
Max
Min/
Min/
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min
—
Agere Systems Inc.
April 5, 2005
Duty Cycle
Duty Cycle
Duty Cycle
45%—55%
45%—55%
45%—55%
45%—55%
45%—55%
Duty Cycle
Duty Cycle
Duty Cycle
40%—60%
40%—60%
40%—60%
45%—55%
45%—55%
40%—60%
40%—60%
40%—60%
40%—60%
40%—60%
40%—60%
40%—60%
40%—60%