TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet - Page 23

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TMXF846221BL-3-DB

Manufacturer Part Number
TMXF846221BL-3-DB
Description
Manufacturer
LSI
Datasheet

Specifications of TMXF846221BL-3-DB

Screening Level
Industrial
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant
Hardware Design Guide, Revision 10
April 5, 2005
Table 2-13. NSMI/STS-1 In
* The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA,
Agere Systems Inc.
AM27, AM26,
AN27, AN26,
on the transmit path are labeled receive. Low-speed outputs, e.g., NSMITXDATA on the receive path are labeled transmit.
AP28, AK24,
AJ24, AP27,
AK23
AP26
AN25
AJ23
Pin
NSMIRXSYNC[3:1]
NSMIRXDATA[3:1]
NSMIRXCLK[3:1]
RXDATAEN[3:1]
Symbol
I/O pd NSMI Receive Clock. Used in the following applications:
I/O pd NSMI Receive Frame Sync. Used in the following applications:
Type
I pd
O
Network Serial Multiplex Interface (NSMI) Receive* Data. Used in
the following applications:
Additionally, it could be used as a SONET compliant STS-1 input signal
to STS1LT from external LIU. For V3.0 devices, these pins may also be
used for DS3 clear channel (positive-rail or single-rail) input data (to the
SPEMPR block).
Additionally, it could be used as an input clock for SONET compliant
STS-1 to STS1LT from external LIU. For V3.0 devices, these pins may
also be used for DS3 clear channel DS3 rate input clock for positive
(and negative) data inputs.
Additionally, it could be used to carry STS-1 input transmit clock for
STS1LTs. For V3.0 devices, these pins may also be used for DS3 clear
channel negative-rail input data (to the SPEMPR block).
NSMI Receive Data Enable. In FRM NSMI mode, this pin is not used.
In the SPEMPR NSMI mode, the signal on this output will be high during
the POH of the SPE.
In M13 NSMI mode, the signal output on this pin goes low during the M1
byte of the first M1 frame of the DS3 frame.
In E13 NSMI mode, the signal output on this pin goes low during the
overhead bytes and control bits of the E3 frame.
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0
51.84 Mbits/s serial data input that is used to bring in multiplexed DS1
or E1 channels to FRM.
STS-1 rate clear-channel receive data to SPEMPR.
DS3/E3 rate clear-channel receive data to M13/E13.
Input (51.84 MHz) for the DS1/E1 application.
Output (51.84 MHz) for the STS-1 rate clear-channel application.
Output (44.736/34.368 MHz) for the DS3/E3 application.
Input receive NSMI control for FRM.
Output receive control frame sync signal for M13/E13.
Output receive control frame sync signal for SPEMPR.
Name/Description
TMXF84622 Ultramapper
23

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