TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet - Page 40

• Manufacturer Part Number: TMXF846221BL-3-DB
• Manufacturer: LSI

Specifications of TMXF846221BL-3-DB

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

TMXF84622 Ultramapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0
4.2 LVDS Interface Characteristics
3.3 V ± 5% V
.
Table 4-4. LVDS Interface dc Characteristics
* The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not
† 250 mV ≤ |V
Notes:
The characteristics in the table above apply under the following conditions:
External LVDS reference chosen (UMPR_LVDS_REF_SEL = 0).
REF10 = 1.0 V ±3% and REF14 = 1.4 V ±3%.
Internal LVDS reference chosen (UMPR_LVDS_REF_SEL = 1).
VDD33 supply controlled to within ± 3%.
When UMPR_LVDS_REF_SEL = 1, the internal reference levels are derived using a resistor ladder from VDD33. These levels will vary as much as the
VDD33 supply does and are therefore only as accurate as the VDD33. If VDD33 cannot be controlled to within ± 3%, one or more IEEE specifications
may be violated. While this may not necessarily lead to data errors during transmission, interoperability issues may arise due to specification noncompli-
ance.
40
40
Input Voltage Range:
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input
Output Voltage:
Output Differential Voltage
Output Offset Voltage
Output Impedance, Single Ended
R
Change in Differential Voltage
Change in Output Offset Voltage
Output Current
Output Current
High (V
Low (V
High (V
Low (V
oscillate.
Impedance
O
Between Complementary States
Between Complementary States
Mismatch Between A and B
IA
OA
IA
OA
or V
A
or V
or V
or V
– V
Parameter
DD
IB
B
, –40 °C to +125 °C junction temperature.
IB
OB
| ≤ 450 mV
OB
)
)
)
)
†
Symbol
I
|∆V
V
SA
V
|V
∆V
∆R
I
V
V
V
R
V
HYST
V
R
SAB
IDTH
V
OH
OD
OS
, I
OL
IH
IL
IN
O
OD
OS
I
O
SB
|
|
Output Buffer Parameters
Input Buffer Parameters
With build-in termination, center-tapped
|V
GPD
Drivers shorted together
V
V
Driver shorted to V
R
R
R
R
R
R
(+V
CM
CM
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
| < 925 mV, dc—1 MHz
Test Conditions
dc— 450 MHz
= 1.0 V and 1.4 V
= 1.0 V and 1.4 V
IDTH
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
) – (–V
IDTH
Hardware Design Guide, Revision 10
SS
)
0.925
1.125
–100
0.25
Min
80
80
—
—
—
—
—
—
—
—
0
Typ
100
100
—
—
—
—
—
—
—
—
—
—
—
—
—
Agere Systems Inc.
April 5, 2005
1.475
1.275
Max
0.45
100
120
120
2.4
—*
10
25
25
24
12
—
—
Unit
mV
mV
mV
mV
mA
mA
%
Ω
Ω
V
V
V
V
V
V