TMXF846221BL-3-DB LSI, TMXF846221BL-3-DB Datasheet - Page 4

• Manufacturer Part Number: TMXF846221BL-3-DB
• Manufacturer: LSI

Specifications of TMXF846221BL-3-DB

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

TMXF84622 Ultramapper
Hardware Design Guide, Revision 9
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1/DS0
April 5, 2005
Table of Contents
(continued)
Tables
Page
Table 5-15. Shared Low-Speed Line Timing Output Specifications .....................................................................................51
Table 5-16. CHIRXGCLK and CHITXGCLK Timing Specifications......................................................................................51
Table 5-17. CHI Interface Timing Specifications ..................................................................................................................52
Table 5-18. PSB Inputs Specifications .................................................................................................................................54
Table 5-19. PSB Output Specifications ................................................................................................................................54
Table 6-1. High-Speed Interface Input Clocks Specifications ..............................................................................................55
Table 6-2. Protection Link Input Clock Specifications ..........................................................................................................55
Table 6-3. DS3/E3/STS-1 Input Clocks Specifications.........................................................................................................55
Table 6-4. DS1/E1 DJA Input Clocks Specifications ............................................................................................................55
Table 6-5. M13/E13 Input Clocks Specifications ..................................................................................................................56
Table 6-6. DS3/E3 DJA Input Clocks Specifications ............................................................................................................56
Table 6-7. LOPOH Input Clock Specifications......................................................................................................................56
Table 6-8. Microprocessor Interface Input Clocks Specifications.........................................................................................56
Table 6-9. Framer PLL Input Clocks Specifications .............................................................................................................56
Table 6-10. CHI Input Clocks Specifications ........................................................................................................................56
Table 6-11. PSB Input Clocks Specifications .......................................................................................................................57
Table 6-12. High-Speed Interface Output Clocks Specifications..........................................................................................57
Table 6-13. Protection Link Output Clocks Specifications....................................................................................................57
Table 6-14. Line Timing Interface Output Clocks Specifications ..........................................................................................57
Table 6-15. TOAC Output Clocks Specifications..................................................................................................................57
Table 6-16. POAC Output Clocks Specifications .................................................................................................................58
Table 6-17. DS3/E3/STS-1 Output Clocks Specifications ....................................................................................................58
Table 6-18. LOPOH Output Clock Specifications.................................................................................................................58
Table 6-19. NSMI Output Clocks Specifications...................................................................................................................58
Table 6-20. Framer PLL Output Clocks Specifications.........................................................................................................58
Table 6-21. Shared Low-Speed Receive Line Input/Output Clocks Specifications ..............................................................58
Table 6-22. Shared Low-Speed Transmit Line Input/Output Clocks Specifications .............................................................59
Table 6-23. NSMI Input/Output Clocks Specifications..........................................................................................................59
Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications ....................................................................61
Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................62
Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................................64
Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications ..................................................................66
Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................67
Table 8-2. Miscellaneous Output Specifications...................................................................................................................67
Table 8-3. General-Purpose Output Specifications ..............................................................................................................67
Table 11-1. Ordering Information .........................................................................................................................................70
Table 13-1. Document Changes...........................................................................................................................................72
4
Agere Systems Inc.