ATA5823-PLQW 80 Atmel, ATA5823-PLQW 80 Datasheet - Page 31
![](/photos/40/57/405769/48pin_qfn_sml.jpg)
ATA5823-PLQW 80
Manufacturer Part Number
ATA5823-PLQW 80
Description
Manufacturer
Atmel
Datasheet
1.ATA5823-PLQW_80.pdf
(98 pages)
Specifications of ATA5823-PLQW 80
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Height (mm)
0.9mm
Product Length (mm)
7mm
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / Rohs Status
Compliant
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9.2
10. Power Supply
Figure 10-1. Power Supply
4829D–RKE–06/06
Basic Clock Cycle of the Digital Circuitry
N_PWR_ON
(Command via SPI)
PWR_ON
DVCC_OK
VSINT
OFFCMD
XTO_OK
VS1
VS2
The complete timing of the digital circuitry is derived from one clock. According to
page
divider.
T
The clock cycle of the Bit-check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see
is defined in control register 4 (see
by the following formulas for further reference:
BR_Range
f
DCLK
DCLK
• Timing of the polling circuit including bit-check
• TX bit rate
&
29, this clock cycle T
=
controls the following application relevant parameters:
f
---------- -
XTO
16
1
1
S
0
0
1
1
S
R
FF1
R
0
1
0
1
IN
Q
Q
no change
0
1
1
DCLK
3.25V typ.
V_REG1
is derived from the crystal oscillator (XTO) in combination with a
EN
Table 12-16 on page
OUT
BR_Range 0: T
BR_Range 1: T
BR_Range 2: T
BR_Range 3: T
SW_AVCC
SW_DVCC
XDCLK
XDCLK
XDCLK
XDCLK
Table 12-19 on page
40). This clock cycle T
ATA5823/ATA5824
= 8
= 4
= 2
= 1
V_Monitor
(1.6V typ.)
T
T
T
T
DCLK
DCLK
DCLK
DCLK
DVCC_OK
(to XTO and
reset logic)
X
X
X
AVCC
DVCC
X
Lim
Lim
Lim
Lim
41) and X
XDCLK
Figure 9-2 on
is defined
Lim
which
31
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