ATA5823-PLQW 80 Atmel, ATA5823-PLQW 80 Datasheet - Page 54

• Manufacturer Part Number: ATA5823-PLQW 80
• Manufacturer: Atmel

Specifications of ATA5823-PLQW 80

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Compliant

Figure 14-1. Flow Chart RX Polling Mode/RX Mode
54
ATA5823/ATA5824
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE -> Low; I
T
Start-up mode:
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bit CLK_ON and OPM0 are set to 1 and the transceiver is set to receiving
mode. Otherwise it is set to Sleep mode or to Start_up mode.
Output level on pin RX_ACTIVE -> High
I
T
Receiving mode:
The incomming data stream is passed via the TX/RX Data Buffer or via pin SDO_TMDO
to the connected microcontroller. If an bit error occurs the transceiver is set back to
Start-up mode.
Output level on pin RX_ACTIVE -> High
I
S
S
Sleep
Bit-check
= I
= I
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE High; I
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE -> High; I
Startup_Sig_proc_X
RX_X
= Sleep
Start RX Mode
NO
written into the TX/RX
RX data stream is
YES
1024
Data Buffer
T
detected ?
OPM0 = 1
Bit error ?
SLEEP
Start bit
?
?
T
DCLK
YES
YES
= 0
YES
Start RX Polling Mode
X
Sleep
NO
NO
NO
S
NO
= I
S
NO
NO
S
= I
IDLE_X
= I
Startup_PLL_X
RX_X
and level on pin CS
Set CLK_ON = 1
T_MODE = 0 and
RX data stream
available on pin
; T
Set OPM0 = 1
T_MODE = 1
SDO_TMDO
P_MODE = 0
= inactive ?
Startup_Sig_proc
Bit check
Set IRQ
OK ?
; I
?
Startup_PLL
YES
YES
Sleep:
X
T
T
T
T
Sleep
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
:
:
:
:
:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control Register 4
Basic clock cycle
798.5
930
546
354
258
Is defined by the selected baud rate range and
T
Baud 0 and Baud 1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
that check despends on the selected bit-rate
range and on T
defined by bit Baud 0 and Baud 1 in Control
Register 6.
If the transparent mode is not active and the
transceiver detects a bit errror after a successful
bit check and before the start bit is detected pin
IRQ will be set to high and the transceiver is set
back to start-up mode.
DCLK
T
T
T
T
.The bit-rate range is defined by bit
DCLK
DCLK
DCLK
DCLK
T
DCLK
(typ)
XDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
. The bit-rate range is
Bit-check
depends on the
Bit-check
4829D–RKE–06/06
) and