TDA5230XT Infineon Technologies, TDA5230XT Datasheet - Page 80

• Manufacturer Part Number: TDA5230XT
• Manufacturer: Infineon Technologies

Specifications of TDA5230XT

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 9.7mm
• Lead Free Status / Rohs Status: Compliant

Figure 39
The synchronization search time T
pattern in an incoming data stream. The minimum value of the search time out length is
the consequence of the system latency time T
The overall system latency time is calculated in two steps: T
input and the filter output (chip data available), and T
and the Framer output (decoded data available).
T
• matched filter computation time
• signal detector delay
T
• Data Slicer computation time
• Framer computation time. The 0.5 T spread is caused by the internal Framer circuit
This means, that for the minimum length of the SYSRCT0, the value 2 2/16 bits plus 0.5
bits, plus the RUNIN length, which is set in the CDR2 register, plus 1.5 bits (to consider
worst case RUNIN patterns) have to be used. To reach all data rate and duty cycle errors
10% of the overall sum must be added.
1) T..nominal duration of one data bit
Data Sheet
1
2
quantization behavior.
latency time include: (T
latency time include: (T
input data
chip-data available
data available
Data Latency
SYSRCT0
RUNIN
T
3
T
1
1
2
=
= 2 2/16 T + 0.5 T)
= 1.5 T to 2.0 T)
T
roundup
2
TSI
3
TSI
is the time the receiver requires for a search for a
(
(
TSI
(
RUNIN
76
1
1)
and RUNIN length.
+
2
2,125
is the time between the Slicer input
+
1
2
T
is the delay between ADC
RUNIN
) 16
2
Functional Description
⋅
PLL re-synchronization
T
Version 4.0, 2007-06-01
2
RUNIN
) 1,1
⋅
RUNIN
)
TDA523x