MT29F4G08ABBDAH4:D Micron Technology Inc, MT29F4G08ABBDAH4:D Datasheet - Page 6

• Manufacturer Part Number: MT29F4G08ABBDAH4:D
• Description: MICMT29F4G08ABBDAH4:D 4G SLC NAND FLASH
• Manufacturer: Micron Technology Inc

List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1 (Top View) ........................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 13
Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 9: Array Organization – MT29F4G08 (x8) .............................................................................................. 16
Figure 10: Array Organization – MT29F4G16 (x16) .......................................................................................... 17
Figure 11: Array Organization – MT29F8G08 and MT29F16G08 (x8) ................................................................. 18
Figure 12: Array Organization – MT29F8G16 (x16) .......................................................................................... 19
Figure 13: Asynchronous Command Latch Cycle ............................................................................................ 21
Figure 14: Asynchronous Address Latch Cycle ................................................................................................ 22
Figure 15: Asynchronous Data Input Cycles .................................................................................................... 23
Figure 16: Asynchronous Data Output Cycles ................................................................................................. 24
Figure 17: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 25
Figure 18: READ/BUSY# Open Drain .............................................................................................................. 26
Figure 19:
Figure 20:
Figure 21: I
Figure 22: I
Figure 23: TC vs. Rp ....................................................................................................................................... 29
Figure 24: R/B# Power-On Behavior ............................................................................................................... 30
Figure 25: RESET (FFh) Operation .................................................................................................................. 34
Figure 26: READ ID (90h) with 00h Address Operation .................................................................................... 35
Figure 27: READ ID (90h) with 20h Address Operation .................................................................................... 35
Figure 28: READ PARAMETER (ECh) Operation .............................................................................................. 39
Figure 29: READ UNIQUE ID (EDh) Operation ............................................................................................... 48
Figure 30: SET FEATURES (EFh) Operation .................................................................................................... 50
Figure 31: GET FEATURES (EEh) Operation .................................................................................................... 51
Figure 32: READ STATUS (70h) Operation ...................................................................................................... 55
Figure 33: READ STATUS ENHANCED (78h) Operation ................................................................................... 56
Figure 34: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 57
Figure 35: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 58
Figure 36: RANDOM DATA INPUT (85h) Operation ........................................................................................ 59
Figure 37: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 61
Figure 38: READ PAGE (00h-30h) Operation ................................................................................................... 65
Figure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 65
Figure 40: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 66
Figure 41: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 67
Figure 42: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 68
Figure 43: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 70
Figure 44: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 72
Figure 45: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 74
Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 74
Figure 47: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 76
Figure 48: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 77
Figure 49: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 78
Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 80
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. J 9/11 EN
t
t
Fall and
Fall and
OL
OL
vs. Rp (1.8V V
vs. Rp (V
t
t
Rise (3.3V V
Rise (1.8V V
CC
= 3.3V V
CC
) ....................................................................................................................... 28
CC
CC
CC
) ................................................................................................................ 27
) ................................................................................................................ 27
) .............................................................................................................. 28
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
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