MAX5866ETM Maxim Integrated Products, MAX5866ETM Datasheet

MAX5866ETM

Manufacturer Part Number

MAX5866ETM

Description

CODECs

Manufacturer

Maxim Integrated Products

Datasheet

1.MAX5866ETM.pdf (26 pages)

Specifications of MAX5866ETM

Lead Free Status / Rohs Status

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The MAX5866 ultra-low-power, highly integrated analog

front end is ideal for portable communication equipment

such as handsets, PDAs, WLAN, and 3G wireless termi-

nals. The MAX5866 integrates dual, 8-bit receive ADCs

and dual, 10-bit transmit DACs while providing the high-

est dynamic performance at ultra-low power. The ADCs’

analog I-Q input amplifiers are fully differential and

accept 1V

phase matching is ±0.2° and amplitude matching is

±0.05dB. The ADCs feature 48dB SINAD and 70.1dBc

spurious-free dynamic range (SFDR) at f

differential with ±400mV full-scale output, and 1.4V com-

mon-mode level. Typical I-Q channel phase matching is

±0.4° and gain matching is ±0.1dB. The DACs also fea-

ture dual, 10-bit resolution with 64.2dBc SFDR, at f

6MHz and f

The ADCs and DACs operate simultaneously or indepen-

dently for frequency-division duplex (FDD) and time-divi-

sion duplex (TDD) modes. A 3-wire serial interface

controls power-down and transceiver modes of opera-

tion. The typical operating power is 96mW at f

60MHz with the ADCs and DACs operating simultane-

ously in transceiver mode. The MAX5866 features an

internal 1.024V voltage reference that is stable over the

entire operating power-supply range and temperature

range. The MAX5866 operates on a +2.7V to +3.3V ana-

log power supply and a +2.7V to +3.3V digital I/O power

supply for logic compatibility. The quiescent current is

12mA in idle mode and 1µA in shutdown mode. The

MAX5866 is specified for the extended (-40°C to +85°C)

temperature range and is available in a 48-pin thin QFN

package.

19-3223; Rev 0; 2/04

Pin Configuration appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

CLK

= 60MHz. The DACs’ analog I-Q outputs are fully

Narrowband/Wideband CDMA Handsets

and PDAs

Fixed/Mobile Broadband Wireless Modems

3G Wireless Terminals

VSAT Modems

P-P

CLK

full-scale signals. Typical I-Q channel

= 60MHz.

________________________________________________________________ Maxim Integrated Products

Performance, 60Msps Analog Front End

General Description

Applications

Ultra-Low-Power, High-Dynamic-

= 25MHz and

CLK

OUT

*EP = Exposed paddle.

MAX5866ETM

Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs

Ultra-Low Power

Excellent Dynamic Performance

Excellent Gain/Phase Match

Internal/External Reference Option

+2.7V to +3.3V Digital Output Level (TTL/CMOS

Compatible)

Multiplexed Parallel Digital Input/Output for

ADCs/DACs

Miniature 48-Pin Thin QFN Package (7mm

Evaluation Kit Available (Order MAX5865EVKIT)

PART

80mW at f

52.5mW at f

Low-Current Idle and Shutdown Modes

48dB SINAD at f

64.2dBc SFDR at f

±0.2° Phase, ±0.05dB Gain at f

REFIN

REFN

REFP

COM

QD+

QA+

QD-

QA-

ID+

IA+

ID-

IA-

CLK

BIAS

AND

REF

ADC

DAC

-40 C to +85 C

= 60MHz (R

TEMP RANGE

= 60MHz (T

Ordering Information

MAX5866

Functional Diagram

OUT

= 25MHz (ADC)

AND SYSTEM

INTERFACE

CONTROL

SERIAL

OUTPUT

INPUT

= 6MHz (DAC)

MUX

ADC

DAC

Mode)

= 25MHz (ADC)

PIN-PACKAGE

48 Thin QFN-EP*

(7mm x 7mm)

DA0–DA7

CLK

DD0–DD9

DIN

SCLK

Features

7mm)

Related parts for MAX5866ETM

MAX5866ETM Summary of contents

Page 1

... Internal/External Reference Option +2.7V to +3.3V Digital Output Level (TTL/CMOS = OUT Compatible) Multiplexed Parallel Digital Input/Output for ADCs/DACs Miniature 48-Pin Thin QFN Package (7mm Evaluation Kit Available (Order MAX5865EVKIT) = CLK PART MAX5866ETM *EP = Exposed paddle. Applications QA+ QD+ QD- REFP COM REFN REFIN Features = 60MHz (R ...

Page 2

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V ...

Page 3

Performance, 60Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 3.0V, internal reference (1.024V tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C Xcvr mode, unless otherwise noted. ...

Page 4

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 3.0V, internal reference (1.024V tude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C Xcvr mode, unless ...

Page 5

Page 6

Page 7

Page 8

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End ( 3.0V, internal reference (1.024V amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C 0.33µF, Xcvr mode +25°C, ...

Page 9

Performance, 60Msps Analog Front End ( 3.0V, internal reference (1.024V amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C 0.33µF, Xcvr mode +25°C, unless otherwise ...

Page 10

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Page 12

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible 11, Analog Supply Voltage. Bypass 33, 39, 43 ...

Page 13

Performance, 60Msps Analog Front End Detailed Description The MAX5866 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conver- sion rate of 60Msps. The ADCs’ analog input amplifiers are ...

Page 14

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed con- version while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock ...

Page 15

Performance, 60Msps Analog Front End ADC System Timing Requirements Figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. Channel IA (CHI) and channel QA (CHQ) are simultaneously sam- pled on the rising edge ...

Page 16

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode V 1.024V, External Reference Mode V DIFFERENTIAL OUTPUT VOLTAGE V 1023 REFDAC × 2.56 1023 V 1021 REFDAC × 2.56 1023 V ...

Page 17

Performance, 60Msps Analog Front End Table 3. MAX5866 Operation Modes FUNCTION DESCRIPTION D evi ce shutd off off, and the ...

Page 18

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End CSS CP SCLK t DS DIN MSB t DH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK 8-BIT DATA DIN DAO–DA7 ID/QD Figure 6. MAX5866 Mode Recovery Timing Diagram ...

Page 19

Performance, 60Msps Analog Front End Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX5866 clock input operates with an ...

Page 20

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End ID+ MAX5866 ID- QD+ QD- Figure 8. Balun-Transformer-Coupled Differential-to-Single- Ended Output Drive for DACs REFP 1kΩ ISO IN 0.1µF 50Ω 22pF 100Ω 1kΩ REFN 0.1µF R ISO 50Ω ...

Page 21

Performance, 60Msps Analog Front End R1 600Ω R2 600Ω R3 600Ω Figure 10. ADC DC-Coupled Differential Drive T/R Figure 11. Typical Application Circuit for TDD ______________________________________________________________________________________________________ Ultra-Low-Power, High-Dynamic 600Ω 600Ω R ISO 22Ω 600Ω 600Ω R8 ...

Page 22

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End Figure 11 illustrates the MAX5866 working with the MAX2820 in TDD mode to provide a complete 802.11b radio front-end solution. Because the MAX5866 DAC has full differential analog outputs with a common-mode level ...

Page 23

Performance, 60Msps Analog Front End Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Offset error (Figure 12a) is the difference ...

Page 24

Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ...

Page 25

Performance, 60Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High-Dynamic- k E/2 (NE- DETAIL ...

Page 26

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Package Information (continued) Printed USA is a registered trademark of Maxim Integrated Products ...

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