MAX5866ETM Maxim Integrated Products, MAX5866ETM Datasheet - Page 22

• Manufacturer Part Number: MAX5866ETM
• Description: CODECs
• Manufacturer: Maxim Integrated Products

Specifications of MAX5866ETM

• Lead Free Status / Rohs Status: No

Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
Figure 11 illustrates the MAX5866 working with the
MAX2820 in TDD mode to provide a complete 802.11b
radio front-end solution. Because the MAX5866 DAC has
full differential analog outputs with a common-mode level
of 1.4V, and the ADC has wide-input common-mode
range, it can interface directly with RF transceivers while
eliminating discrete components and amplifiers used for
level-shifting circuits. Also, the DAC’s full dynamic range
is preserved because the internally generated common-
mode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5866
ADC has 1V
mon-mode levels of V
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
The MAX5866 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surface-
mount devices for minimum inductance. Bypass V
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF capacitor. Bypass OV
ceramic capacitor in parallel with a 2.2µF capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33µF ceramic capacitor. Bypass REFIN to GND with
a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
Figure 12a. Integral Nonlinearity
22
___________________________________________________________________________________________________
P-P
Grounding, Bypassing, and
7
6
5
4
3
2
1
0
000
full-scale range and accepts input com-
001
DD
010
DIGITAL INPUT CODE
AT STEP
001 (1/4 LSB )
/ 2 (±200mV). These features
011
DD
100
AT STEP
011 (1/2 LSB )
to OGND with a 0.1µF
Board Layout
101
110
111
DD
to
the MAX5866 exposed backside paddle to the GND
plane. Join the two ground planes at a single point so
the noisy digital ground currents do not interfere with
the analog ground plane. The ideal location for this
connection can be determined experimentally at a
point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90° turns.
ADC and DAC Static Parameter Definitions
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the end-point method. (DAC Figure 12a).
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
Figure 12b. Differential Nonlinearity
Dynamic Parameter Definitions
6
5
4
3
2
1
0
000
001
DIGITAL INPUT CODE
010
Differential Nonlinearity (DNL)
1 LSB
011
Integral Nonlinearity (INL)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
100
101
1 LSB