MAX5866ETM Maxim Integrated Products, MAX5866ETM Datasheet - Page 19

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MAX5866ETM

Manufacturer Part Number
MAX5866ETM
Description
CODECs
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX5866ETM

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Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5866 clock input operates
with an OV
±10% duty cycle.
The MAX5866 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature range. The REFIN input pro-
vides two modes of reference operation. The voltage at
REFIN (V
In internal reference mode, connect REFIN to V
is an internally generated 0.512V. COM, REFP, and REFN
are low-impedance outputs with V
= V
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with V
V
V
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor. In this mode, the DAC’s full-scale output volt-
age and common-mode voltage are proportional to the
external reference. For example, if the V
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or to ±440mV, and
the common-mode voltage increases by 10%.
Table 4. Reference Modes
REFP
REFIN
1.024V ±10%
>0. 8 x V
DD
V
REFIN
= V
/ 2 + V
/ 4. Bypass REFP, REFN, and COM each with a
REFIN
DD
DD
DD
) sets reference operation mode (Table 4).
/ 2 + V
/ 2 voltage threshold and accepts a 50%
REF
Internal reference mode. V
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor.
Buffered external reference mode. An
external 1.024V ±10% reference voltage
is applied to REFIN. V
generated to be V
REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a
0.1µF capacitor.
______________________________________________________________________________________
/ 2, and V
Performance, 60Msps Analog Front End
REFIN
Reference Configurations
REFERENCE MODE
/ 4, and V
REFN
COM
REFIN
= V
REF
Ultra-Low-Power, High-Dynamic-
DD
REFN
COM
= V
/ 2. Bypass REFP,
is internally
REF
/ 2 - V
DD
= V
= V
is internally
/ 2, V
DD
REFIN
DD
REF
DD
. V
REFP
/ 2 -
/ 2,
REF
/ 2.
is
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
provides a V
transformer can be used, or a step-up transformer can
be selected to reduce the drive requirements. In gener-
al, the MAX5866 provides better SFDR and THD with
fully differential input signals than single-ended signals,
especially for high input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing com-
pared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5866 DACs’ differential
analog outputs to single ended.
Figure 7. Balun-Transformer-Coupled Single-Ended-to-
Differential Input Drive for ADCs
V
V
IN
IN
Using Balun Transformer AC-Coupling
0.1µF
0.1µF
DD
Applications Information
/ 2 DC level shift to the input. A 1:1
0.33µF
0.33µF
25Ω
25Ω
25Ω
25Ω
0.1µF
0.1µF
22pF
22pF
22pF
22pF
IA+
COM
IA-
QA+
QA-
MAX5866
19

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