MAX5866ETM Maxim Integrated Products, MAX5866ETM Datasheet - Page 15

• Manufacturer Part Number: MAX5866ETM
• Description: CODECs
• Manufacturer: Maxim Integrated Products

Specifications of MAX5866ETM

• Lead Free Status / Rohs Status: No

Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sam-
pled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
Figure 2. ADC Transfer Function
Figure 3. ADC System Timing Diagram
DA0–DA7
CHQ
CLK
1111 1111
1111 1110
1111 1101
1000 0001
1000 0000
0111 1111
0000 0011
0000 0010
0000 0001
0000 0000
CHI
t
DOQ
-128
D0Q
-127
1 LSB =
-126 -125
______________________________________________________________________________________
ADC System Timing Requirements
Performance, 60Msps Analog Front End
2 x V
V
REF
256
D1I
REF
INPUT VOLTAGE (LSB)
t
DOI
-1
D1Q
(COM)
0
+1
V
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
REF
D2I
Ultra-Low-Power, High-Dynamic-
V
= V
REF
REFP
+125
- V
+126
REFN
D2Q
+127
+128
(COM)
D3I
D3Q
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
The 10-bit DACs are capable of operating with clock
speeds up to 60MHz. The DAC’s digital inputs, DD0–DD9,
are multiplexed on a single 10-bit bus. The voltage refer-
ence determines the data converters’ full-scale output
voltages. See the Reference Configurations section for
setting reference voltage. The DACs utilize a current-array
technique with a 1mA (with 1.024V reference) full-scale
output current driving a 400Ω internal resistor resulting in
a ±400mV full-scale differential output voltage. The
MAX5866 is designed for differential output only and is
not intended for single-ended application. The analog
outputs are biased at 1.4V common mode and designed
to drive a differential input stage with input impedance
≥70kΩ. This simplifies the analog interface between RF
quadrature upconverters and the MAX5866. RF upcon-
verters require a 1.3V to 1.5V common-mode bias. The
internal DC common-mode bias eliminates discrete level-
setting resistors and code-generated level-shifting while
preserving the full dynamic range of each transmit DAC.
Table 2 shows the output voltage vs. input code.
D4I
D4Q
D5I
D5Q
Dual 10-Bit DAC
D6I
D6Q
15