PIC16LF1933-E/MV Microchip Technology, PIC16LF1933-E/MV Datasheet - Page 118

• Manufacturer Part Number: PIC16LF1933-E/MV
• Description: IC MCU 8BIT 7KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1933-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1933
12.1
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in
following functions can be moved between different
pins.
• SS (Slave Select)
• P2B output
• CCP2/P2A output
• CCP3/P3A output
• Timer1 gate
• SR Latch SRNQ output
• Comparator C2 output
REGISTER 12-1:
DS41575A-page 118
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Alternate Pin Function
Register
Unimplemented: Read as ‘0’.
CCP3SEL: CCP3 Input/Output Pin Selection bit
0 = CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9
1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
T1GSEL: Timer1 Gate Input Pin Selection bit
0 = T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
1 = T1G function is on RC4/SDI/SDA/T1G/SEG11
P2BSEL: CCP2 PWM B Output Pin Selection bit
0 = P2B function is on RC0/T1OSO/T1CKI/P2B
1 = P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1
SRNQSEL: SR Latch nQ Output Pin Selection bit
0 = SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/V
1 = SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/V
C2OUTSEL: Comparator C2 Output Pin Selection bit
0 = C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/V
1 = C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/V
SSSEL: SS Input Pin Selection bit
0 = SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/V
1 = SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/V
CCP2SEL: CCP2 Input/Output Pin Selection bit
0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A
1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3
CCP3SEL
R/W-0/0
12-1. For this device family, the
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
T1GSEL
R/W-0/0
P2BSEL
R/W-0/0
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
SRNQSEL
R/W-0/0
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
C2OUTSEL
R/W-0/0
CAP
CAP
CAP
CAP
 2011 Microchip Technology Inc.
CAP
CAP
R/W-0/0
SSSEL
CCP2SEL
R/W-0/0
bit 0