PIC16LF1933-E/MV Microchip Technology, PIC16LF1933-E/MV Datasheet - Page 269

• Manufacturer Part Number: PIC16LF1933-E/MV
• Description: IC MCU 8BIT 7KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1933-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 24-2:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
R/C/HS-0/0
WCOL
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
R/C/HS-0/0
2
2
2
2
SSPOV
C mode:
C mode:
C Slave mode:
C Master mode:
started
SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if
only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software).
Transmit mode (must be cleared in software).
SSPCON1: SSP CONTROL REGISTER 1
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
SSPEN
R/W-0/0
CKP
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
HS = Bit is set by hardware
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
2
C conditions were not valid for a transmission to be
R/W-0/0
PIC16(L)F1933
SSPM<3:0>
C = User cleared
R/W-0/0
DS41575A-page 269
(2)
(3)
R/W-0/0
bit 0