DF2117RVLP20HV Renesas Electronics America, DF2117RVLP20HV Datasheet - Page 147
DF2117RVLP20HV
Manufacturer Part Number
DF2117RVLP20HV
Description
MCU 16BIT FLASH 3V 160K 144-LGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2117RVLP20HV
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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2.2.38
MAC (Multiply and ACcumulate)
Operation
(EAn)
MAC register
ERn
ERm + 2
Assembly-Language Format
MAC @ERn+, @ERm+
Operand Size
—
Description
This instruction performs signed multiplication on two 16-bit operands at addresses given by the
contents of general registers ERn and ERm, adds the 32-bit product to the contents of the MAC
register, and stores the sum in the MAC register. After this operation, ERn and ERm are both
incremented by 2.
The operation can be carried out in saturating or non-saturating mode, depending on the MACS
bit in a system control register. (SYSCR)
See the relevant hardware manual for further information.
In non-saturating mode, MACH and MACL are concatenated to store a 42-bit result. The value of
bit 41 is copied into the upper 22 bits of MACH as a sign extension.
In saturating mode, only MACL is valid, and the result is limited to the range from H'80000000
(minimum value) to H'7FFFFFFF (maximum value). If the result overflows in the negative
direction, H'80000000 (the minimum value) is stored in MACL. If the result overflows in the
positive direction, H'7FFFFFFF (the maximum value) is stored in MACL. The LSB of the MACH
register indicates the status of the overflow flag (V-MULT) in the multiplier. Other bits retain
their previous contents.
This instruction is supported only by the H8S/2600 CPU.
+ 2
(EAm) + MAC register
MAC
ERn
ERm
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rev. 4.00 Feb 24, 2006 page 131 of 322
—
I
UI H
—
Section 2 Instruction Descriptions
—
Multiply and Accumulate
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U
—*
N
REJ09B0139-0400
—*
Z
—* —
V
C
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