DF2117RVLP20HV Renesas Electronics America, DF2117RVLP20HV Datasheet - Page 236

• Manufacturer Part Number: DF2117RVLP20HV
• Description: MCU 16BIT FLASH 3V 160K 144-LGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117RVLP20HV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 2 Instruction Descriptions
2.2.60 (5)
SHLR (SHift Logical Right)
Operation
ERd (right logical shift)
Assembly-Language Format
SHLR.L ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right.
The least significant bit (bit 0) shifts into the carry flag. The most significant bit (bit 31) is cleared
to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 220 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHLR (L)
Mnemonic
0
SHLR.L
MSB
b31
ERd
Operands
ERd
.
. . . . . .
.
1st byte
1
.
.
1
Condition Code
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 0.
.
2nd byte
3
.
Instruction Format
cleared to 0.
—
I
0 erd
UI H
—
LSB
b0
—
3rd byte
—
U
C
N
0
4th byte
Z
Shift Logical
V
0
States
No. of
C
1