DF2117RVLP20HV Renesas Electronics America, DF2117RVLP20HV Datasheet - Page 22

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DF2117RVLP20HV

Manufacturer Part Number
DF2117RVLP20HV
Description
MCU 16BIT FLASH 3V 160K 144-LGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2117RVLP20HV

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Section 1 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per
16 bits (figure 1.2). The exception vector table differs depending on the microcontroller. Refer to
the relevant microcontroller hardware manual for further information.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a
16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF.
Note that this area is also used for the exception vector table.
Rev. 4.00 Feb 24, 2006 page 6 of 322
REJ09B0139-0400
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Figure 1.2 Exception Vector Table (Normal Mode)
Power-on reset exception vector
Manual reset exception vector
(Reserved for system use)
Exception vector 1
Exception vector 2
Exception
vector table

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